Datasheet

AT89C51AC3

4383D–8051–02/08

Functional Description

Figure 44 shows a detailed structure of the SPI Module.

Figure 44. SPI Module Block Diagram

Operating Modes The Serial Peripheral Interface can be configured in one of the two modes: Master mode

or Slave mode. The configuration and initialization of the SPI Module is made through

two registers:

• The Serial Peripheral Control register (SPCON)

• The Serial Peripheral Status and Control Register (SPSCR)

Once the SPI is configured, the data exchange is made using:

• The Serial Peripheral DATa register (SPDAT)

During an SPI transmission, data is simultaneously transmitted (shifted out serially) and

received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam-

pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows

individual selection of a Slave SPI device; Slave devices that are not selected do not

interfere with SPI bus activities.

Shift Register

234567

Internal Bus

Control

Logic

MISO

MOSI

SCK

Clock

Logic

SPI Interrupt

8-bit bus

1-bit signal

FCLK

Receive Data Register

SPDAT

SPI

Control

Transmit Data Register

- MODFSPIF OVR SPTE UARTM

SPTEIE

MODFIE

SPSCR

SPEN MSTRSPR2 SSDIS CPOL CPHA SPR1 SPR0

SPCON

Request

PERIPH