Datasheet

45
AT89C51AC3
4383D–8051–02/08
FSTA Register
Table 14. FSTA Register
FSTA Register (S:D3h)
Flash Status Register
Reset Value= 0000 0000b
Mapping of the Memory Space By default, the user space is accessed by MOVC A, @DPTR instruction for read only.
The column latches space is made accessible by setting the FPS bit in FCON register.
Writing is possible from 0000h to FFFFh, address bits 6 to 0 are used to select an
address within a page while bits 15 to 7 are used to select the programming address of
the page.
Setting FPS bit takes precedence on the EXTRAM bit in AUXR register.
The other memory spaces (user, extra row, hardware security) are made accessible in
the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor-
dance with Table 15. A MOVC instruction is then used for reading these spaces.
Table 15. FM0 Blocks Select Bits
Notes: 1. The column latches reset is a new option introduced in the AT89C51AC3, and is not
available in T89C51CC01/2
Launching Programming FPL3:0 bits in FCON register are used to secure the launch of programming. A specific
sequence must be written in these bits to unlock the write protection and to launch the
programming. This sequence is 5xh followed by Axh. Table 16 summarizes the memory
spaces to program according to FMOD1:0 bits.
7 6 5 4 3 2 1 0
SEQERR FLOAD
Bit
Number
Bit
Mnemonic Description
7-2 unusesd
1 SEQERR
Flash activation sequence error
Set by hardware when the flash activation sequence(MOV FCON 5X and MOV
FCON AX )is not correct (See Error Repport Section)
Clear by software or clear by hardware if the last activation sequence was
correct (previous error are canceled)
0 FLOAD
Flash Colums latch loaded
Set by hardware when the first data is loaded in the column latches.
Clear by hardware when the activation sequence suceed (flash write sucess, or
reset column latch success)
FMOD1 FMOD0 FM0 Adressable space
0 0 User (0000h-FFFFh)
0 1 Extra Row(FF80h-FFFFh)
1 0 Hardware Security Byte (0000h)
1 1 Column latches reset (note1)