Datasheet

39
AT89C51AC3
4383D–8051–02/08
External Code Memory Access
Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as
the bus control signals (PSEN#, and ALE).
Figure 21 shows the structure of the external address bus. P0 carries address A7:0
while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 21
describes the external memory interface signals.
Figure 21. External Code Memory Interface Structure
External Bus Cycles This section describes the bus cycles the AT89C51AC3 executes to fetch code (see
Figure 22) in the external program/code memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator
clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor-
mation on X2 mode see section “Clock “.
For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized
form and do not provide precise timing information.
For bus cycling parameters refer to the ‘AC-DC parameters’ section.
Table 12. External Code Memory Interface Signals
Signal
Name Type Description
Alternate
Function
A15:8 O
Address Lines
Upper address lines for the external bus.
P2.7:0
AD7:0 I/O
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
P0.7:0
ALE O
Address Latch Enable
ALE signals indicates that valid address information are available on lines
AD7:0.
-
PSEN# O
Program Store Enable Output
This signal is active low during external code fetch or external code read
(MOVC instruction).
-
Flash
EPROM
AT89C51AC3
P2
P0
AD7:0
A15:8
A7:0
A15:8
D7:0
A7:0
ALE
Latch
OEPSEN#