Datasheet

AT89C51AC3

4383D–8051–02/08

Entering Power-Down Mode To enter Power-Down mode, set PD bit in PCON register. The AT89C51AC3 enters the

Power-Down mode upon execution of the instruction that sets PD bit. The instruction

that sets PD bit is the last instruction executed.

Exiting Power-Down Mode

Note: If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until

VCC is restored to the normal operating level.

There are two ways to exit the Power-Down mode:

1. Generate an enabled external interrupt.

– The AT89C51AC3 provides capability to exit from Power-Down using INT0#,

INT1#.

Hardware clears PD bit in PCON register which starts the oscillator and

restores the clocks to the CPU and peripherals. Using INTx# input,

execution resumes when the input is released (see Figure 19). Execution

resumes with the interrupt service routine. Upon completion of the interrupt

service routine, program execution resumes with the instruction immediately

following the instruction that activated Power-Down mode.

Note: The external interrupt used to exit Power-Down mode must be configured as level sensi-

tive (INT0# and INT1#) and must be assigned the highest priority. In addition, the

duration of the interrupt must be long enough to allow the oscillator to stabilize. The exe-

cution will only resume when the interrupt is deasserted.

Note: Exit from power-down by external interrupt does not affect the

SFRs

nor the internal RAM

content.

Figure 19. Power-Down Exit Waveform Using INT1:0#

2. Generate a reset.

– A logic high on the RST pin clears PD bit in PCON register directly and

asynchronously. This starts the oscillator and restores the clock to the CPU

and peripherals. Program execution momentarily resumes with the

instruction immediately following the instruction that activated Power-Down

mode and may continue for a number of clock cycles before the internal

reset algorithm takes control. Reset initializes the AT89C51AC3 and vectors

the CPU to address 0000h.

Note: During the time that execution resumes, the internal RAM cannot be accessed; however,

it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port

pins, the instruction immediately following the instruction that activated the Power-Down

mode should not write to a Port pin or to the external RAM.

Note: Exit from power-down by reset redefines all the

SFRs

, but does not affect the internal

RAM content.

INT1:0#

OSC

Power-down phase Oscillator restart phase Active phaseActive phase