Datasheet

25
AT89C51AC3
4383D–8051–02/08
Registers Table 6. PSW Register
PSW (S:8Eh)
Program Status Word Register
Reset Value = 0000 0000b
Table 7. AUXR Register
AUXR (S:8Eh)
Auxiliary Register
7 6 5 4 3 2 1 0
CY AC F0 RS1 RS0 OV F1 P
Bit
Number
Bit
Mnemonic Description
7 CY
Carry Flag
Carry out from bit 1 of ALU operands.
6 AC
Auxiliary Carry Flag
Carry out from bit 1 of addition operands.
5 F0 User Definable Flag 0.
4-3 RS1:0
Register Bank Select Bits
Refer to Table 4 for bits description.
2 OV
Overflow Flag
Overflow set by arithmetic operations.
1 F1 User Definable Flag 1
0 P
Parity Bit
Set when ACC contains an odd number of 1’s.
Cleared when ACC contains an even number of 1’s.
7 6 5 4 3 2 1 0
- - M0 XRS2 XRS1 XRS0 EXTRAM A0
Bit
Number
Bit
Mnemonic Description
7-6 -
Reserved
The value read from these bits are indeterminate. Do not set this bit.
5 M0
Stretch MOVX control:
the RD/ and the WR/ pulse length is increased according to the value of M0.
M0 Pulse length in clock period
0 6
1 30