Datasheet

AT89C51AC3

4383D–8051–02/08

Table 3. CKCON1 Register

CKCON1 (S:9Fh)

Clock Control Register 1

Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit

has no effect.

Reset Value = XXXX XXX0b

7 6 5 4 3 2 1 0

SPIX2

Bit

Number

Bit

Mnemonic Description

7-1 -

Reserved

The value read from these bits is indeterminate. Do not set these bits.

0 SPIX2

SPI clock

(1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.