Datasheet

16
AT89C51AC3
4383D–8051–02/08
Figure 5. Clock CPU Generation Diagram
XTAL1
XTAL2
PD
PCON.1
CPU Core
1
0
÷ 2
PERIPH
CLOCK
Clock
Peripheral
CPU
CLOCK
CPU Core Clock Symbol
X2
CKCON.0
X2B
Hardware byte
WDX2
CKCON0.6
PCAX2
CKCON0.5
SIX2
CKCON0.4
T2X2
CKCON0.3
T1X2
CKCON0.2
T0X2
CKCON0.1
IDL
PCON.0
1
0
÷ 2
1
0
÷ 2
1
0
÷ 2
1
0
÷ 2
1
0
÷ 2
1
0
÷ 2
X2
CKCON.0
FWd Clock
FPca Clock
FUart Clock
FT2 Clock
FT1 Clock
FT0 Clock
and ADC
On RESET
1
0
÷ 2
FSPIClock
SPIX2
CKCON1.0
Clock Symbol