Datasheet

133
AT89C51AC3
4383D–8051–02/08
Flash/EEPROM Memory Table 83. Timing Symbol Definitions
Table 84. Memory AC Timing
VDD = 3V to 5.5V, TA = -40 to +85°C
Figure 68. Flash Memory – ISP Waveforms
Figure 69. Flash Memory – Internal Busy Waveforms
Signals Conditions
S (Hardware
condition)
PSEN#,EA L Low
R RST V Valid
B FBUSY flag X No Longer Valid
Symbol Parameter Min Typ Max Unit
T
SVRL
Input PSEN# Valid to RST Edge 50 ns
T
RLSX
Input PSEN# Hold after RST Edge 50 ns
T
BHBL
Flash/EEPROM Internal Busy
(Programming) Time
10 ms
RST
T
SVRL
PSEN#1
T
RLSX
FBUSY bit
T
BHBL