Datasheet

118
AT89C51AC3
4383D–8051–02/08
Table 68. IPL1 Register
IPL1 (S:F8h)
Interrupt Priority Low Register 1
Reset Value = XXXX 0X0Xb
bit addressable
7 6 5 4 3 2 1 0
- - - - SPIL - PADCL -
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 SPIL
SPI Interrupt Priority Level Less Significant Bit
Refer to SPIH for priority level.
2 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1 PADCL
ADC Interrupt Priority Level Less Significant Bit
Refer to PSPIH for priority level.
0 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.