Datasheet

116
AT89C51AC3
4383D–8051–02/08
Table 66. IEN1 Register
IEN1 (S:E8h)
Interrupt Enable Register
Reset Value = xxxx 0x0xb
bit addressable
7 6 5 4 3 2 1 0
- - - - ESPI - EADC -
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 ESPI
SPI Interrupt Enable bit
Clear to disable the SPI interrupt.
Set to enable the SPI interrupt.
2 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1 EADC
ADC Interrupt Enable bit
Clear to disable the ADC interrupt.
Set to enable the ADC interrupt.
0 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.