Datasheet

100
AT89C51AC3
4383D–8051–02/08
PCA Registers Table 50. CMOD Register
CMOD (S:D9h)
PCA Counter Mode Register
Reset Value = 00XX X000b
7 6 5 4 3 2 1 0
CIDL WDTE - - - CPS1 CPS0 ECF
Bit
Number
Bit
Mnemonic Description
7 CIDL
PCA Counter Idle Control bit
Clear to let the PCA run during Idle mode.
Set to stop the PCA when Idle mode is invoked.
6 WDTE
WatchDog Timer Enable
Clear to disable WatchDog Timer function on PCA Module 4,
Set to enable it.
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2-1 CPS1:0
EWC Count Pulse Select bits
CPS1 CPS0 Clock source
0 0 Internal Clock, FPca/6
0 1 Internal Clock, FPca/2
1 0 Timer 0 overflow
1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca/4)
0 ECF
Enable PCA Counter Overflow Interrupt bit
Clear to disable CF bit in CCON register to generate an interrupt.
Set to enable CF bit in CCON register to generate an interrupt.