Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PLCC 52 (19.2x19.2) 8-Bit 60 MHz I/O number 36

Rev. 4383D–8051–02/08

Features

•

80C51 Core Architecture

•

256 Bytes of On-chip RAM

•

2048 Bytes of On-chip ERAM

•

64K Bytes of On-chip Flash Memory

– Data Retention: 10 Years at 85°C

– Read/Write Cycle: 100K

•

Boot Code Section with Independent Lock Bits

•

2K Bytes of On-chip Flash for Bootloader

•

In-System Programming by On-Chip UART Boot Program and IAP Capability

•

2K Bytes of On-chip EEPROM

Read/Write Cycle: 100K

•

Integrated Power Monitor (POR: PFD) To Supervise Internal Power Supply

•

14-sources 4-level Interrupts

•

Three 16-bit Timers/Counters

•

Full Duplex UART Compatible 80C51

•

High-speed Architecture

– In Standard Mode:

40 MHz (Vcc 3V to 5.5V, both Internal and external code execution)

60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

– In X2 mode (6 Clocks/machine cycle)

20 MHz (Vcc 3V to 5.5V, both Internal and external code execution)

30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

•

Five Ports: 32 + 4 Digital I/O Lines

•

Five-channel 16-bit PCA with

– PWM (8-bit)

– High-speed Output

– Timer and Edge Capture

•

Double Data Pointer

•

21-bit WatchDog Timer (7 Programmable Bits)

•

A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs

•

SPI Interface (PLCC52 and VPFP64 packages only)

•

On-chip Emulation Logic (Enhanced Hook System)

•

Power Saving Modes

– Idle Mode

– Power-down Mode

•

Power Supply: 3 volts to 5.5 volts

•

Temperature Range: Industrial (-40° to +85°C)

•

Packages: VQFP44, PLCC44, VQFP64, PLCC52

Description

The AT89C51AC3 is a high performance Flash version of the 80C51 single chip 8-bit

microcontrollers.

In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.

Besides the AT89C51AC3 provides 64K Bytes of Flash memory including In-System

Programming (ISP) and IAP, 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and

2048 byte ERAM.

Primary attention is paid to the reduction of the electro-magnetic emission of

AT89C51AC3.

Enhanced 8-bit

Microcontroller

with 64KB Flash

Memory

AT89C51AC3

Summary of content (140 pages)

PAGE 1
Features • • • • • • • • • • • • • • • • • • • • • • • • 80C51 Core Architecture 256 Bytes of On-chip RAM 2048 Bytes of On-chip ERAM 64K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K Boot Code Section with Independent Lock Bits 2K Bytes of On-chip Flash for Bootloader In-System Programming by On-Chip UART Boot Program and IAP Capability 2K Bytes of On-chip EEPROM Read/Write Cycle: 100K Integrated Power Monitor (POR: PFD) To Supervise Internal Power Supply 14-so
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T2 T2EX PCA ECI Vss Vcc TxD RxD Block Diagram XTAL1 RAM 256x8 UART XTAL2 ALE C51 CORE PSEN ERAM 2048 Flash Boot EE 64k x 8 loader PROM 2kx8 2kx8 PCA Timer2 IB-bus CPU EA Notes: 2 Emul Unit 10 bit ADC SPI Interface MOSI SCK MISO P4(2) P3 P2 INT1 INT0 T1 T0 RESET WR Parallel I/O Ports and Ext. Bus Watch Dog Port 0 Port 1 Port 2 Port 3 Port 4 P1(1) INT Ctrl P0 Timer 0 Timer 1 RD 1. 8 analog Inputs/8 Digital I/O 2.
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AT89C51AC3 6 5 4 3 2 1 44 43 42 41 40 P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 Pin Configuration 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 PLCC44 ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 P2.0/A8 P1.3/AN3/CEX0 P1.2/AN2/ECI P1.1/AN1/T2EX P1.0/AN 0/T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P3.6/WR P3.7/RD P4.0 P4.1 P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.
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3 2 VCC XTAL1 XTAL2 VAGND RESET VSS TESTI VCC 5 4 1 52 51 50 49 48 47 8 46 9 10 45 44 11 43 12 42 13 41 14 PLCC52 ALE PSEN P0.7/AD7 P0.6/AD6 NC P0.5/AD5 P0.4 /AD4 P0.3 /AD3 P0.2 /AD2 P0.1 /AD1 15 40 39 16 38 17 37 18 36 19 35 P4.4/MOSI P0.0 /AD0 34 P2.0/A8 21 22 23 24 25 26 27 28 29 30 31 32 33 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P4.2/MISO 20 P3.6/WR P3.7/RD P4.0 P4.1 P2.7/A15 P2.6/A14 NC P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1/SS 6 VAREF P1.3/AN3/CEX0 P1.
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AT89C51AC3 Pin Name Type Description VSS GND Circuit ground TESTI I Must be connected to VSS Supply Voltage VCC VAREF Reference Voltage for ADC VAGND Reference Ground for ADC P0.0:7 I/O Port 0: Is an 8-bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in this state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory.
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Pin Name Type P3.0:7 I/O Description Port 3: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups.
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AT89C51AC3 Pin Name Type RESET I/O Reset: A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC. O ALE: An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access.
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Figure 1. Port 1, Port 3 and Port 4 Structure VCC ALTERNATE OUTPUT FUNCTION READ LATCH INTERNAL BUS READ PIN Port 0 and Port 2 P1.x P3.x P4.x D P1.X Q P3.X P4.X LATCH CL WRITE TO LATCH Note: INTERNAL PULL-UP (1) ALTERNATE INPUT FUNCTION The internal pull-up can be disabled on P1 when analog function is selected. Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port 0, shown in Figure 3, differs from the other Ports in not having internal pull-ups.
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AT89C51AC3 Figure 3. Port 2 Structure ADDRESS HIGH/ CONTROL VDD INTERNAL PULL-UP (2) READ LATCH P2.x (1) 1 INTERNAL BUS WRITE TO LATCH D P2.X LATCH Q 0 READ PIN Notes: 1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus drivers. 2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for memory bus cycle.
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write the new byte back to the latch. These Read-Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of an external bipolar transistor can not rise above the transistor’s base-emitter junction voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU to read the Port at the pin are misinterpreted as logic zero.
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AT89C51AC3 SFR Mapping The Special Function Registers (SFRs) of the AT89C51AC3 fall into the following categories: Mnemonic Add Name 7 6 5 4 3 2 1 0 ACC E0h Accumulator – – – – – – – – B F0h B Register – – – – – – – – PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P SP 81h Stack Pointer – – – – – – – – DPL 82h Data Pointer Low byte – – – – – – – – – – – – – – – – LSB of DPTR DPH 83h Data Pointer High byte MSB of DPTR Mnemonic
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Mnemonic Add Name 7 6 5 4 3 2 1 0 T2CON C8h Timer/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# T2MOD C9h Timer/Counter 2 Mode – – – – – – T2OE DCEN RCAP2H Timer/Counter 2 CBh Reload/Capture High byte – – – – – – – – RCAP2L Timer/Counter 2 CAh Reload/Capture Low byte – – – – – – – – WDTRST A6h WatchDog Timer Reset – – – – – – – – WDTPRG A7h WatchDog Timer Program – – – – – S2 S1 S0 Mnemonic Add Name 7 6 5 4 3 2
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AT89C51AC3 Mnemonic Add Name 7 6 5 4 3 2 1 0 IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0 IEN1 E8h Interrupt Enable Control 1 – – – – ESPI – EADC – IPL0 B8h Interrupt Priority Control Low 0 – PPC PT2 PS PT1 PX1 PT0 PX0 IPH0 B7h Interrupt Priority Control High 0 – PPCH PT2H PSH PT1H PX1H PT0H PX0H IPL1 F8h Interrupt Priority Control Low 1 – – – – SPIL – PADCL – IPH1 F7h Interrupt Priority Control High1 – – – – SPIH
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Table 1.
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AT89C51AC3 Clock The AT89C51AC3 core needs only 6 clock periods per machine cycle. This feature, called”X2”, provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. • Saves power consumption while keeping the same CPU power (oscillator power saving). • Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes. • Increases CPU power by 2 while keeping the same crystal frequency.
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Figure 5. Clock CPU Generation Diagram X2B Hardware byte PCON.0 On RESET IDL X2 CKCON.0 XTAL1 ÷2 CPU Core Clock 0 1 XTAL2 CPU CLOCK PD CPU Core Clock Symbol and ADC PCON.1 ÷2 1 FT0 Clock 0 ÷2 1 FT1 Clock 0 ÷2 1 FT2 Clock 0 ÷2 1 FUart Clock 0 ÷2 1 FPca Clock 0 ÷2 1 FWd Clock 0 ÷2 1 FSPIClock 0 X2 PERIPH CLOCK CKCON.0 SPIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 CKCON1.0 CKCON0.6 CKCON0.5 CKCON0.4 CKCON0.3 CKCON0.2 CKCON0.
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AT89C51AC3 Figure 6. Mode Switching Waveforms XTAL1 XTAL1/2 X2 bit CPU clock STD Mode Note: X2 Mode STD Mode In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms.
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Registers Table 2. CKCON0 Register CKCON0 (S:8Fh) Clock Control Register 7 6 5 4 3 2 1 0 - WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Number 7 - Reserved The value read from this bits is indeterminate. Do not set this bit. 6 WDX2 WatchDog clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 5 PCAX2 Programmable Counter Array clock (1) Clear to select 6 clock periods per peripheral clock cycle.
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AT89C51AC3 Table 3. CKCON1 Register CKCON1 (S:9Fh) Clock Control Register 1 7 6 5 4 3 2 1 0 SPIX2 Bit Number 7-1 0 Note: Bit Mnemonic Description - SPIX2 Reserved The value read from these bits is indeterminate. Do not set these bits. SPI clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect.
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Data Memory The AT89C51AC3 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: • the lower 128 Bytes RAM segment. • the upper 128 Bytes RAM segment. • the expanded 2048 Bytes RAM segment (ERAM). 2. The external space. A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode. Figure 8 shows the internal and external data memory spaces organization.
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AT89C51AC3 Internal Space Lower 128 Bytes RAM The lower 128 Bytes of RAM (see Figure 8) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4 banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 6) select which bank is in use according to Table 4.
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External Space Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD#, WR#, and ALE). Figure 10 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 5 describes the external memory interface signals. Figure 10.
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AT89C51AC3 Figure 11. External Data Read Waveforms CPU Clock ALE RD#1 P0 P2 Notes: DPL or Ri P2 D7:0 DPH or P22 1. RD# signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. Figure 12. External Data Write Waveforms CPU Clock ALE WR#1 P0 P2 Notes: DPL or Ri P2 D7:0 DPH or P22 1. WR# signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content.
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Dual Data Pointer Description The AT89C51AC3 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR 0 and DPTR 1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Figure 8) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 13). Figure 13.
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AT89C51AC3 Registers Table 6. PSW Register PSW (S:8Eh) Program Status Word Register 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P Bit Number Bit Mnemonic Description 7 CY Carry Flag Carry out from bit 1 of ALU operands. 6 AC Auxiliary Carry Flag Carry out from bit 1 of addition operands. 5 F0 User Definable Flag 0. 4-3 RS1:0 2 OV Overflow Flag Overflow set by arithmetic operations. 1 F1 User Definable Flag 1 0 P Parity Bit Set when ACC contains an odd number of 1’s.
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Bit Number 4-2 1 0 Bit Mnemonic Description XRS1-0 EXTRAM A0 ERAM size: Accessible size of the ERAM XRS 2:0 ERAM size 000 256 Bytes 001 512 Bytes 010 768 Bytes 011 1024 Bytes 100 1792 Bytes 101 2048 Bytes (default configuration after reset) 110 Reserved 111 Reserved Internal/External RAM (00h - FFh) access using MOVX @ Ri/@ DPTR 0 - Internal ERAM access using MOVX @ Ri/@ DPTR. 1 - External data memory access.
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AT89C51AC3 Power Monitor The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an internal reset to them. By generating the Reset the Power Monitor insures a correct start up when AT89C51CC03 is powered up.
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Figure 15. Power Fail Detect Vcc t Reset Vcc When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input. The internal reset will remain asserted until the Xtal1 levels are above and below VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is de-asserted.
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AT89C51AC3 Reset Introduction The reset sources are : Power Management, Hardware Watchdog, PCA Watchdog and Reset input. Figure 16. Reset Schematic Power Monitor Hardware Watchdog Internal Reset PCA Watchdog RST Reset Input The Reset input can be used to force a reset pulse longer than the internal reset controlled by the Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to VCC as shown in Figure 17.
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Reset Output As detailed in Section “Watchdog Timer”, page 79, the WDT generates a 96-clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit, a 1 kΩ resistor must be added as shown Figure 18. Figure 18.
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AT89C51AC3 Power Management Introduction Two power reduction modes are implemented in the AT89C51AC3. The Idle mode and the Power-Down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section “Clock”, page 15. Idle Mode Idle mode is a power reduction mode that reduces the power consumption. In this mode, program execution halts.
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Entering Power-Down Mode To enter Power-Down mode, set PD bit in PCON register. The AT89C51AC3 enters the Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. Exiting Power-Down Mode Note: If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until VCC is restored to the normal operating level. There are two ways to exit the Power-Down mode: 1. Generate an enabled external interrupt.
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AT89C51AC3 Table 9.
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Registers Table 10. PCON Register PCON (S87:h) Power configuration Register 7 6 5 4 3 2 1 0 - - - - GF1 GF0 PD IDL Bit Number Bit Mnemonic Description Reserved The value read from these bits is indeterminate. Do not set these bits. 7-4 - 3 GF1 General Purpose flag 1 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode.
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AT89C51AC3 EEPROM Data Memory The 2-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/ERAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming).
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Examples ;*F*************************************************************************;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read.
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AT89C51AC3 Registers Table 11. EECON Register EECON (S:0D2h) EEPROM Control Register 7 6 5 4 3 2 1 0 EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY Bit Number Bit Mnemonic 7-4 EEPL3-0 Programming Launch command bits Write 5Xh followed by AXh to EEPL to launch the programming. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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Program/Code Memory The AT89C51AC3 implement 64K Bytes of on-chip program/code memory. Figure 20 shows the partitioning of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD voltage.
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AT89C51AC3 External Code Memory Access Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (PSEN#, and ALE). Figure 21 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 21 describes the external memory interface signals. Figure 21.
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Figure 22. External Code Fetch Waveforms CPU Clock ALE PSEN# P0 D7:0 PCL P2 PCH Flash Memory Architecture D7:0 PCL D7:0 PCH PCH AT89C51AC3 features two on-chip Flash memories: • Flash memory FM0: containing 64K Bytes of program memory (user space) organized into 128 byte pages, • Flash memory FM1: 2K Bytes for boot loader and Application Programming Interfaces (API).
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AT89C51AC3 Figure 24.
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FM0 Memory Architecture The Flash memory is made up of 4 blocks (see Figure 23): • The memory array (user space) 64K Bytes • The Extra Row • The Hardware security bits • The column latch registers User Space This space is composed of a 64K Bytes Flash memory organized in 512 pages of 128 Bytes. It contains the user’s application code. Extra Row (XRow) This row is a part of FM0 and has a size of 128 Bytes. The extra row may contain information for boot loader usage.
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AT89C51AC3 Code executing from Cross Flash Memory Access FM0 (user Flash) FM1 (boot Flash) Action FM0 (user Flash) FM1 (boot Flash) Read ok - Load column latch ok - Write - - Read ok ok Load column latch ok - Write ok - Read (a) - External memory Load column latch - - EA = 0 Write - - (a) Depend upon general lock bit configuration.
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Overview of FM0 Operations Flash Registers (SFR) The CPU interfaces to the flash memory through the FCON register, AUXR1 register and FSTA register. These registers are used to map the column latches, HSB, extra row and EEDATA in the working data or code space. FCON Register Table 13.
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AT89C51AC3 FSTA Register Table 14.
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Table 16. Programming Spaces Write to FCON FPL3:0 FPS FMOD1 FMOD0 Operation 5 X 0 0 No action A X 0 0 Write the column latches in user space 5 X 0 1 No action A X 0 1 Write the column latches in extra row space User Extra Row Hardware Security Byte 5 X 1 0 No action A X 1 0 Write the fuse bits space Reset 5 X 1 1 No action Columns Latches A X 1 1 Reset the column latches Notes: Status of the Flash Memory 1.
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AT89C51AC3 order. The page address of the last address loaded in the column latches will be used for the whole page. When programming is launched, an automatic erase of the locations loaded in the column latches is first performed, then programming is effectively done. Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page Notes: 1. : If no bytes are written in the column latches the SEQERR bit in the FSTA register will be set. 2.
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Figure 25. Column Latches Loading Procedure Column Latches Loading Save and Disable IT EA = 0 Column Latches Mapping FCON = 08h (FPS=1) Data Load DPTR = Address ACC = Data Exec: MOVX @DPTR, A Last Byte to load? Data memory Mapping FCON = 00h (FPS = 0) Restore IT Note: The last page address used when loading the column latch is the one used to select the page programming address.
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AT89C51AC3 Figure 26. Flash and Extra Row Programming Procedure Flash Spaces Programming Column Latches Loading see Figure 25 Save and Disable IT EA = 0 Launch Programming FCON = 5xh FCON = Axh FBusy Cleared? Clear Mode FCON = 00h End Programming Restore IT Hardware Security Byte The following procedure is used to program the Hardware Security Byte space and is summarized in Figure 27: • Set FPS and map Hardware byte (FCON = 0x0C) • Save and disable the interrupts. • Load DPTR at address 0000h.
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Figure 27. Hardware Programming Procedure Flash Spaces Programming Save and Disable IT EA = 0 Save and Disable IT EA = 0 FCON = 0Ch Launch Programming FCON = 54h FCON = A4h Data Load DPTR = 00h ACC = Data Exec: MOVX @DPTR, A FBusy Cleared? End Loading Restore IT Clear Mode FCON = 00h End Programming RestoreIT Reset the Column Latches An automatic reset of the column latches is performed after a successful Flash write sequence.
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AT89C51AC3 Power Down Request Before entering in Power Down (Set bit PD in PCON register) the user should check that no write sequence is in progress (check BUSY=0), then check that the column latches are reset (FLOAD=0 in FSTA register. Launch a reset column latches to clear FLOAD if necessary. Reading the Flash Spaces User The following procedure is used to read the User space: • Read one byte in Accumulator by executing MOVC A,@A+DPTR with A+DPTR=read@.
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Table 17. Program Lock Bit Program Lock Bits Security level LB0 LB1 LB2 1 U U U No program lock features enabled. U MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further parallel programming of the Flash is disabled. 2 P U Protection Description ISP and software programming with API are still allowed.
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AT89C51AC3 Operation Cross Memory Access Space addressable in read and write are: • RAM • ERAM (Expanded RAM access by movx) • XRAM (eXternal RAM) • EEPROM DATA • FM0 ( user flash ) • Hardware byte • XROW • Boot Flash • Flash Column latch The table below provide the different kind of memory which can be accessed from different code location. Table 18.
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Sharing Instructions Table 19. Instructions shared XRAM Action RAM ERAM EEPROM DATA Boot FLASH FM0 Hardware Byte XROW Read MOV MOVX MOVX MOVC MOVC MOVC MOVC Write MOV MOVX MOVX - by cl by cl by cl Note: by cl : using Column Latch Table 20. Read MOVX A, @DPTR Flash EEE bit in FPS in XRAM EECON Register FCON Register ENBOOT EA ERAM 0 0 X X OK 0 1 X X OK 1 0 X X 1 1 X X EEPROM DATA Column Latch OK OK Table 21.
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AT89C51AC3 Table 22.
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In-System Programming (ISP) With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the AT89C51AC3 allows the system engineer the development of applications with a very high level of flexibility. This flexibility is based on the possibility to alter the customer program at any stages of a product’s life: • Before assembly the 1st personalization of the product by programming in the FM0 and if needed also a customized Boot loader in the FM1.
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AT89C51AC3 Boot Loader Jump Bit (BLJB): - This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1. - BLJB = 0 on parts delivered with bootloader programmed. - To read or modify this bit, the APIs are used. Boot Vector Address (SBV): - This byte contains the MSB of the user boot loader address in FM0. - The default value of SBV is FFh (no user boot loader in FM0). - To read or modify this byte, the APIs are used.
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Figure 30. Hardware Boot Process Algorithm bit ENBOOT in AUXR1 register is initialized with BLJB. RESET Hardware Hardware condition? No ENBOOT = 0 PC = 0000h No ENBOOT = 1 PC = F800h FCON = 00h Yes FCON = F0h BLJB = = 0 ? Yes Software ENBOOT = 1 PC = F800h Application in FM0 Application Programming Interface Boot Loader in FM1 Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages.
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AT89C51AC3 Hardware Security Byte Table 24. Hardware Security Byte 7 6 5 4 3 2 1 0 X2B BLJB - - - LB2 LB1 LB0 Bit Number Bit Mnemonic Description 7 X2B X2 Bit Set this bit to start in standard mode Clear this bit to start in X2 mode. 6 BLJB Boot Loader JumpBit - 1: To start the user’s application on next RESET (@0000h) located in FM0, - 0: To start the boot loader(@F800h) located in FM1. 5-3 - 2-0 LB2:0 Reserved The value read from these bits are indeterminate.
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Serial I/O Port The AT89C51AC3 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements: • Framing error detection • Automatic address recognition Figure 31.
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AT89C51AC3 Figure 33. UART Timing in Mode 1 RXD D0 D1 D2 D3 D4 D5 D6 D7 Data byte Start bit Stop bit RI SMOD0=X FE SMOD0=1 Figure 34. UART Timing in Modes 2 and 3 RXD D0 Start bit D1 D2 D3 D4 Data byte D5 D6 D7 D8 Ninth Stop bit bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).
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Given Address Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
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AT89C51AC3 For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. Registers Table 25.
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Table 26. SADEN Register SADEN (S:B9h) Slave Address Mask Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number Bit Mnemonic Description Mask Data for Slave Individual Address 7-0 Reset Value = 0000 0000b Not bit addressable Table 27. SADDR Register SADDR (S:A9h) Slave Address Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number Bit Mnemonic Description Slave Individual Address 7-0 Reset Value = 0000 0000b Not bit addressable Table 28.
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AT89C51AC3 Table 29. PCON Register PCON (S:87h) Power Control Register 7 6 5 4 3 2 1 0 SMOD1 SMOD0 – POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. 5 - 4 POF Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage.
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Timers/Counters The AT89C51AC3 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin.
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AT89C51AC3 Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0 register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register (see Figure 35). The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments TH0 register. Figure 35.
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Mode 2 (8-bit Timer with AutoReload) Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads from TH0 register (see Figure 37). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next reload value may be changed at any time by writing it to TH0 register. Figure 37.
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AT89C51AC3 Timer 1 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The following comments help to understand the differences: • Timer 1 functions as either a Timer or event Counter in three modes of operation. Figure 35 to Figure 37 show the logical configuration for modes 0, 1, and 2. Timer 1’s mode 3 is a hold-count mode. • Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 31) and bits 2, 3, 6 and 7 of TCON register (see Figure 30).
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Interrupt Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register. Figure 39. Timer Interrupt System Timer 0 Interrupt Request TF0 TCON.5 ET0 IEN0.1 Timer 1 Interrupt Request TF1 TCON.7 ET1 IEN0.3 Registers Table 30.
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AT89C51AC3 Table 31. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register 7 6 5 4 3 2 1 0 GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 Bit Number Bit Mnemonic Description 7 GATE1 Timer 1 Gating Control Bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. 6 C/T1# Timer 1 Counter/Timer Select Bit Clear for Timer operation: Timer 1 counts the divided-down system clock.
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Table 32. TH0 Register TH0 (S:8Ch) Timer 0 High Byte Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number Bit Mnemonic Description High Byte of Timer 0. 7:0 Reset Value = 0000 0000b Table 33. TL0 Register TL0 (S:8Ah) Timer 0 Low Byte Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number Bit Mnemonic Description Low Byte of Timer 0. 7:0 Reset Value = 0000 0000b Table 34.
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AT89C51AC3 Table 35. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number 7:0 Bit Mnemonic Description Low Byte of Timer 1.
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Timer 2 The AT89C51AC3 timer 2 is compatible with timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 that are cascade- connected. It is controlled by T2CON register (See Table ) and T2MOD register (See Table 38). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FT2 clock/6 (timer operation) or external pin T2 (counter operation) as timer clock. Setting TR2 allows TL2 to be incremented by the selected input.
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AT89C51AC3 Programmable ClockOutput In clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 41). The input clock increments TL2 at frequency FOSC/2. The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts.
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Registers Table 36. T2CON Register T2CON (S:C8h) Timer 2 Control Register 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Number 7 Bit Mnemonic Description TF2 Timer 2 Overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. Must be cleared by software. Set by hardware on timer 2 overflow. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
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AT89C51AC3 Table 37. T2MOD Register T2MOD (S:C9h) Timer 2 Mode Control Register 7 6 5 4 3 2 1 0 - - - - - - T2OE DCEN Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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Table 39. TL2 Register TL2 (S:CCh) Timer 2 Low Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7-0 Low Byte of Timer 2. Reset Value = 0000 0000b Not bit addressable Table 40. RCAP2H Register RCAP2H (S:CBh) Timer 2 Reload/Capture High Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7-0 High Byte of Timer 2 Reload/Capture. Reset Value = 0000 0000b Not bit addressable Table 41.
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AT89C51AC3 Watchdog Timer AT89C51AC3 contains a powerful programmable hardware Watchdog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc = 12MHz in X1 mode. This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a Watchdog Timer reset register (WDTRST) and a Watchdog Timer programming (WDTPRG) register.
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Watchdog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 42.
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AT89C51AC3 Watchdog Timer During Power-down Mode and Idle In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of exiting Power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, the Watchdog is disabled. Exiting Power-down with an interrupt is significantly different.
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Table 45. WDTRST Register WDTRST (S:A6h Write only) Watchdog Timer Enable Register 7 6 5 4 3 2 1 0 – – – – – – – – Bit Number 7 Bit Mnemonic Description - Watchdog Control Value Reset Value = 1111 1111b Note: 82 The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in sequence without instruction between these two sequences.
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AT89C51AC3 Serial Port Interface (SPI) The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs.
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In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSCR) to prevent multiple masters from driving MOSI and SCK (see Error conditions). A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state. The SS pin could be used as a general-purpose if the following conditions are met: • The device is configured as a Master and the SSDIS control bit in SPCON is set.
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AT89C51AC3 Functional Description Figure 44 shows a detailed structure of the SPI Module. Figure 44.
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When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 45). Figure 45.
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AT89C51AC3 Figure 46. Data Transmission Format (CPHA = 0) SCK Cycle Number 1 2 3 4 5 6 7 8 MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB bit6 bit5 bit4 bit3 bit2 bit1 LSB SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) MSB SS (to Slave) Capture Point Figure 47.
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When a transmission is in progress a new data can be queued and sent as soon as transmission has been completed. So it is possible to transmit bytes without latency, useful in some applications. The SPTE bit in SPSCR is set as long as the transmission buffer is free. It means that the user application can write SPDAT with the data to be transmitted until the SPTE becomes cleared. Figure 49 shows a queuing transmission in master mode. Once the Byte 1 is ready, it is immediately sent on the bus.
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AT89C51AC3 Error Conditions The following flags in the SPSCR register indicate the SPI error conditions: Mode Fault Error (MODF) Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. • Mode fault detection in Master mode: MODF is set to warn that there may be a multi-master conflict for system control.
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Figure 51. Mode Fault Conditions in Slave Mode 0 SCK cycle # SCK (from master) MOSI (from master) 0 OverRun Condition 2 3 4 MSB B6 B5 B4 1 z 0 1 z 0 MISO (from slave) 1 z 0 SS (slave) 1 z 0 MSB MSB MODF detected Note: 1 B6 MODF detected when SS is discarded (SS disabled) it is not possible to detect a MODF error in slave mode because the SPI is internally selected. Also the SS pin becomes a general purpose I/O.
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AT89C51AC3 Figure 52. SPI Interrupt Requests Generation SPIF SPTEIE SPI CPU Interrupt Request SPTE MODFIE MODF Registers Three registers in the SPI module provide control, status and data storage functions. These registers are describe in the following paragraphs.
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Bit Number Bit Mnemonic 3 CPOL Description Clock Polarity Cleared to have the SCK set to ’0’ in idle state. Set to have the SCK set to ’1’ in idle state. Clock Phase 2 Cleared to have the data sampled when the SCK leaves the idle state (see CPOL). CPHA Set to have the data sampled when the SCK returns to idle state (see CPOL).
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AT89C51AC3 Bit Number Bit Mnemonic Description Mode Fault - Set by hardware to indicate that the SS pin is in inappropriate logic level (in both master and slave modes). - Cleared by hardware when reading SPSCR 4 MODF When MODF error occurred: - In slave mode: SPI interface ignores all transmitted data while SS remains high. A new transmission is perform as soon as SS returns low. - In master mode: SPI interface is disabled (SPEN=0, see description for SPEN bit in SPCON register).
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Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules.
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AT89C51AC3 Figure 53. PCA Timer/Counter To PCA modules FPca/6 overflow FPca/2 CH T0 OVF It CL 16 bit up counter P1.2 CIDL WDTE CF CR CPS1 CPS0 ECF CMOD 0xD9 Idle CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 The CMOD register includes three additional bits associated with the PCA. • The CIDL bit which allows the PCA to stop during idle mode. • The WDTE bit which enables or disables the WatchDog function on module 4.
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Each module in the PCA has a special function register associated with it (CCAPM0 for module 0 ...). The CCAPM0:4 registers contain the bits that control the mode that each module will operate in. • The ECCF bit enables the CCF flag in the CCON register to generate an interrupt when a match or compare occurs in the associated module. • The PWM bit enables the pulse width modulation mode.
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AT89C51AC3 Figure 55. PCA Capture Mode PCA Counter CH CL (8bits) (8bits) CEXn n = 0, 4 CCAPnH CCAPnL PCA Interrupt Request CCFn CCON - 0CAPPn CAPNn 000 ECCFn 0 7 CCAPMn Register (n = 0, 4) 16-bit Software Timer Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register.
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High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set. Figure 57.
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AT89C51AC3 Figure 58. PCA PWM Mode CCAPnH CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL CCAPnL “0” CL < CCAPnL 8-Bit Comparator CL (8 bits) CEX CL > = CCAPnL “1” PCA WatchDog Timer ECOMn PWMn CCAPMn.6 CCAPMn.1 An on-board WatchDog timer is available with the PCA to improve system reliability without increasing chip count. WatchDog timers are useful for systems that are sensitive to noise, power glitches, or electrostatic discharge.
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PCA Registers Table 50. CMOD Register CMOD (S:D9h) PCA Counter Mode Register 7 6 5 4 3 2 1 0 CIDL WDTE - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic Description PCA Counter Idle Control bit Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked. 7 CIDL 6 WDTE 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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AT89C51AC3 Table 51. CCON Register CCON (S:D8h) PCA Counter Control Register 7 6 5 4 3 2 1 0 CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 Bit Number Bit Mnemonic Description 7 CF PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA interrupt request if the ECF bit in CMOD register is set. Must be cleared by software. 6 CR PCA Timer/Counter Run Control bit Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on.
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Table 52. CCAPnH Registers CCAP0H (S:FAh) CCAP1H (S:FBh) CCAP2H (S:FCh) CCAP3H (S:FDh) CCAP4H (S:FEh) PCA High Byte Compare/Capture Module n Register (n=0..4) 7 6 5 4 3 2 1 0 CCAPnH 7 CCAPnH 6 CCAPnH 5 CCAPnH 4 CCAPnH 3 CCAPnH 2 CCAPnH 1 CCAPnH 0 Bit Number 7:0 Bit Mnemonic Description CCAPnH 7:0 High byte of EWC-PCA comparison or capture values Reset Value = 0000 0000b Table 53.
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AT89C51AC3 Table 54. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) CCAPM2 (S:DCh) CCAPM3 (S:DDh) CCAPM4 (S:DEh) PCA Compare/Capture Module n Mode registers (n=0..4) 7 6 5 4 3 2 1 0 - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Bit Number 7 Bit Mnemonic Description - Reserved The Value read from this bit is indeterminate. Do not set this bit. 6 ECOMn Enable Compare Mode Module x bit Clear to disable the Compare function. Set to enable the Compare function.
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Table 55. CH Register CH (S:F9h) PCA Counter Register High Value 7 6 5 4 3 2 1 0 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 Bit Number 7:0 Bit Mnemonic Description CH 7:0 High byte of Timer/Counter Reset Value = 0000 00000b Table 56.
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AT89C51AC3 Analog-to-Digital Converter (ADC) This section describes the on-chip 10 bit analog-to-digital converter of the AT89C51AC3. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10-bit cascaded potentiometric ADC. Two kinds of conversion are available: - Standard conversion (8 bits). - Precision conversion (10 bits).
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Figure 59. ADC Description ADCON.5 ADCON.3 ADEN ADSST ADC Interrupt Request ADCON.4 ADEOC ADC CLOCK CONTROL EADC AN0/P1.0 000 AN1/P1.1 001 AN2/P1.2 010 AN3/P1.3 011 AN4/P1.4 100 AN5/P1.5 101 AN6/P1.6 110 AN7/P1.7 IEN1.1 ADCIN 8 ADDH 2 ADDL + SAR - AVSS Sample and Hold 111 10 R/2R DAC SCH2 SCH1 SCH0 ADCON.2 ADCON.1 ADCON.0 VAREF VAGND Figure 60 shows the timing diagram of a complete conversion.
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AT89C51AC3 ADC Converter Operation A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). After completion of the A/D conversion, the ADSST bit is cleared by hardware. The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is set, an interrupt occur when flag ADEOC is set (see Figure 62). Clear this flag for rearming the interrupt.
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Figure 61. A/D Converter clock CPU CLOCK ÷2 Prescaler ADCLK ADC Clock A/D CPU Core Clock Symbol Converter ADC Standby Mode When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode its power dissipation is about 1 µW. IT ADC Management An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software. Figure 62.
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AT89C51AC3 EADC = 1 // clear the field SCH[2:0] ADCON and = F8h // Select the channel ADCON | = channel // Start conversion in precision mode ADCON | = 48h Note: to enable the ADC interrupt: EA = 1 109 4383D–8051–02/08
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Registers Table 58. ADCF Register ADCF (S:F6h) ADC Configuration 7 6 5 4 3 2 1 0 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 Bit Number 7-0 Bit Mnemonic Description CH 0:7 Channel Configuration Set to use P1.x as ADC input. Clear to use P1.x as standart I/O port. Reset Value =0000 0000b Table 59.
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AT89C51AC3 Table 60. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler 7 6 5 4 3 2 1 0 - - - PRS 4 PRS 3 PRS 2 PRS 1 PRS 0 Bit Number Bit Mnemonic Description 7-5 - 4-0 PRS4:0 Reserved The value read from these bits are indeterminate. Do not set these bits. Clock Prescaler See Note (1) Reset Value = XXX0 0000b Note: 1. In X1 mode: For PRS > 0 FADC = FXTAL 4xPRS For PRS = 0 FADC = FXTAL 128 In X2 mode: For PRS > 0 FADC = FXTAL 2xPRS For PRS = 0 FADC = FXTAL 64 Table 61.
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Bit Number Bit Mnemonic Description 7-2 - 1-0 ADAT1:0 Reserved The value read from these bits are indeterminate. Do not set these bits.
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AT89C51AC3 Interrupt System Introduction The Micro-controller has a total of 9 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), a serial port interrupt, a PCA, a timer overrun interrupt and an ADC. These interrupts are shown below. Figure 63. Interrupt Control System INT0# 00 01 10 11 External Interrupt 0 Highest Priority Interrupts EX0 00 01 10 11 IEN0.0 Timer 0 ET0 INT1# External Interrupt 1 00 01 10 11 IEN0.1 EX1 00 01 10 11 IEN0.
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Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all the interrupts at the same time. Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the bit values and priority levels associated with each combination. Table 63.
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AT89C51AC3 Registers Table 65. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register 7 6 5 4 3 2 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7 EA Enable All Interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 6 EC PCA Interrupt Enable Clear to disable the PCA interrupt. Set to enable the PCA interrupt.
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Table 66. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register 7 6 5 4 3 2 1 0 - - - - ESPI - EADC - Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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AT89C51AC3 Table 67. IPL0 Register IPL0 (S:B8h) Interrupt Enable Register 7 6 5 4 3 2 1 0 - PPC PT2 PS PT1 PX1 PT0 PX0 Bit Number Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. 7 - 6 PPC PCA Interrupt Priority bit Refer to PPCH for priority level 5 PT2 Timer 2 Overflow Interrupt Priority bit Refer to PT2H for priority level. 4 PS Serial Port Priority bit Refer to PSH for priority level.
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Table 68. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register 1 7 6 5 4 3 2 1 0 - - - - SPIL - PADCL - Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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AT89C51AC3 Table 69. IPL0 Register IPH0 (B7h) Interrupt High Priority Register 7 6 5 4 3 2 1 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H Bit Number 7 6 5 4 3 2 1 0 Bit Mnemonic Description - Reserved The value read from this bit is indeterminate. Do not set this bit.
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Table 70. IPH1 Register IPH1 (S:F7h) Interrupt High Priority Register 1 7 6 5 4 3 2 1 0 - - - - SPIH - PADCH - Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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AT89C51AC3 Electrical Characteristics Absolute Maximum Ratings Note: Ambiant Temperature Under Bias: I = industrial ....................................................... -40°C to 85°C Storage Temperature .................................... -65°C to + 150°C Voltage on VCC from VSS ......................................-0.5V to + 6V Voltage on Any Pin from VSS ..................... -0.5V to VCC + 0.
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Table 71. DC Parameters in Standard Voltage (Continued) Symbol ICC Notes: Parameter Typ(5) Min ICCOP = 0.4 Frequency (MHz) + 8 Power Supply Current ICCIDLE = 0.2 Frequency (MHz) + 8 Max Unit mA Test Conditions Vcc = 5.5V(1)(2) 1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 67.), VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure 64.). 2.
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AT89C51AC3 Figure 65. ICC Test Condition, Idle Mode VCC ICC VCC VCC P0 RST EA XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL All other pins are disconnected. Figure 66. ICC Test Condition, Power-Down Mode VCC ICC VCC VCC P0 RST (NC) EA XTAL2 XTAL1 All other pins are disconnected. VSS Figure 67. Clock Signal Waveform for ICC Tests in Active and Idle Modes VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. DC Parameters for A/D Converter 0.7VCC 0.2VCC-0.1 Table 72.
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AC Parameters Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example: TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA = -40°C to +85°C; VSS = 0V; VCC = 3V to 5.5V; F = 0 to 40 MHz.
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AT89C51AC3 External Program Memory Characteristics Table 73. Symbol Description Symbol T Parameter Oscillator clock period TLHLL ALE pulse width TAVLL Address Valid to ALE TLLAX Address Hold After ALE TLLIV ALE to Valid Instruction In TLLPL ALE to PSEN TPLPH PSEN Pulse Width TPLIV PSEN to Valid Instruction In TPXIX Input Instruction Hold After PSEN TPXIZ Input Instruction Float After PSEN TAVIV Address to Valid Instruction In TPLAZ PSEN Low to Address Float Table 74.
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Table 75. AC Parameters for a Variable Clock Symbol Type Standard Clock X2 Clock X parameter Units TLHLL Min 2T-x T-x 10 ns TAVLL Min T-x 0.5 T - x 15 ns TLLAX Min T-x 0.5 T - x 15 ns TLLIV Max 4T-x 2T-x 30 ns TLLPL Min T-x 0.5 T - x 10 ns TPLPH Min 3T-x 1.5 T - x 20 ns TPLIV Max 3T-x 1.5 T - x 40 ns TPXIX Min x x 0 ns TPXIZ Max T-x 0.5 T - x 7 ns TAVIV Max 5T-x 2.
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AT89C51AC3 External Data Memory Characteristics Table 76. Symbol Description Symbol Parameter TRLRH RD Pulse Width TWLWH WR Pulse Width TRLDV RD to Valid Data In TRHDX Data Hold After RD TRHDZ Data Float After RD TLLDV ALE to Valid Data In TAVDV Address to Valid Data In TLLWL ALE to WR or RD TAVWL Address to WR or RD TQVWX Data Valid to WR Transition TQVWH Data set-up to WR High TWHQX Data Hold After WR TRLAZ RD Low to Address Float TWHLH RD or WR High to ALE high Table 77.
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Table 78. AC Parameters for a Variable Clock 128 Symbol Type Standard Clock X2 Clock X parameter Units TRLRH Min 6T-x 3T-x 20 ns TWLWH Min 6T-x 3T-x 20 ns TRLDV Max 5T-x 2.5 T - x 25 ns TRHDX Min x x 0 ns TRHDZ Max 2T-x T-x 20 ns TLLDV Max 8T-x 4T -x 40 ns TAVDV Max 9T-x 4.5 T - x 60 ns TLLWL Min 3T-x 1.5 T - x 25 ns TLLWL Max 3T+x 1.5 T + x 25 ns TAVWL Min 4T-x 2T-x 25 ns TQVWX Min T-x 0.5 T - x 15 ns TQVWH Min 7T-x 3.
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AT89C51AC3 External Data Memory Write Cycle TWHLH ALE PSEN TLLWL TWLWH WR TQVWX TLLAX PORT 0 A0-A7 TWHQX TQVWH DATA OUT TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 External Data Memory Read Cycle TWHLH TLLDV ALE PSEN TLLWL RD TRLRH TRHDZ TAVDV TLLAX PORT 0 TAVWL PORT 2 TRHDX A0-A7 ADDRESS OR SFR-P2 DATA IN TRLAZ ADDRESS A8-A15 OR SFR P2 Serial Port Timing – Shift Register Mode Table 79.
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Table 80. AC Parameters for a Fix Clock (F = 40 MHz) Symbol Min Max TXLXL 300 ns TQVHX 200 ns TXHQX 30 ns TXHDX 0 ns TXHDV Units 117 ns Table 81.
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AT89C51AC3 External Clock Drive Waveforms VCC-0.5V 0.45V 0.7VCC 0.2VCC-0.1 TCHCX TCLCH TCLCX TCHCL TCLCL AC Testing Input/Output Waveforms VCC -0.5V 0.2 VCC + 0.9 INPUT/OUTPUT 0.2 VCC - 0.1 0.45V AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. Float Waveforms FLOAT VOH - 0.1 V VOL + 0.1 V VLOAD VLOAD + 0.1 V VLOAD - 0.
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Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
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AT89C51AC3 Flash/EEPROM Memory Table 83. Timing Symbol Definitions Signals Conditions S (Hardware condition) PSEN#,EA L Low R RST V Valid B FBUSY flag X No Longer Valid Table 84. Memory AC Timing VDD = 3V to 5.5V, TA = -40 to +85°C Symbol Parameter Min Typ TSVRL Input PSEN# Valid to RST Edge 50 ns TRLSX Input PSEN# Hold after RST Edge 50 ns TBHBL Flash/EEPROM Internal Busy (Programming) Time 10 Max Unit ms Figure 68.
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Ordering Information Table 85.
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AT89C51AC3 Package Drawing VQFP44 135 4383D–8051–02/08
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PLCC44 136 AT89C51AC3 4383D–8051–02/08
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AT89C51AC3 VQFP64 137 4383D–8051–02/08
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PLCC52 138 AT89C51AC3 4383D–8051–02/08
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AT89C51AC3 Document Revision History Changes from 4383A 10/04 - 4383B 01/05 1. Various minor corrections made throughout the document. Changes from 4383B 01/05 to 4383C 11/05 1. Added Green product ordering information. Changes from 4383C 11/05 to 4383D 02/08 1. Removed non green products from ordering information. 2. Clarification to Mode Switching Waveforms diagram. See page 17.
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