Datasheet

A/T89C51AC2

4127H–8051–02/08

Figure 19. External Code Fetch Waveforms

Flash Memory

Architecture

A/T89C51AC2 features two on-chip Flash memories:

• Flash memory FM0:

containing 32 KB of program memory (user space) organized into 128 byte pages,

• Flash memory FM1:

2 KB for boot loader and Application Programming Interfaces (API).

The FM0 can be program by both parallel programming and Serial In-System-Program-

ming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP

mode is detailed in the "In-System-Programming" section.

All Read/Write access operations on Flash Memory by user application are managed by

a set of API described in the "In-System-Programming" section.

Figure 20. Flash Memory Architecture

ALE

PSEN#

PCL

PCHPCH

PCLD7:0 D7:0

PCH

D7:0

CPU Clock

7FFFh

32 KB

Flash memory

FM0

0000h

Hardware Security (1 byte)

Column Latches (128 Bytes)

user space

Extra Row (128 Bytes)

2 KB

Flash memory

FM1

boot space

FFFFh

F800h

FM1 mapped between F800h and

FFFFh when bit ENBOOT is set in

AUXR1 register