Datasheet

113
A/T89C51AC2
4127H–8051–02/08
Flash/EEPROM Memory Table 88. Timing Symbol Definitions
Table 89. Memory AC Timing
VDD = 5V ± 10%, TA = -40 to +85°C
Figure 54. Flash Memory – ISP Waveforms
Figure 55. Flash Memory – Internal Busy Waveforms
A/D Converter
Table 90. AC Parameters for A/D Conversion
Signals Conditions
S (Hardware
condition)
PSEN#,EA L Low
R RST V Valid
B FBUSY flag X No Longer Valid
Symbol Parameter Min Typ Max Unit
T
SVRL
Input PSEN# Valid to RST Edge 50 ns
T
RLSX
Input PSEN# Hold after RST Edge 50 ns
T
BHBL
Flash/EPROM Internal Busy
(Programming) Time
10 ms
N
FCY
Number of Flash/EEPROM Erase/Write
Cycles
100 000 cycles
T
FDR
Flash/EEPROM Data Retention Time 10 years
RST
T
SVRL
PSEN#1
T
RLSX
FBUSY bit
T
BHBL
Symbol Parameter Min Typ Max Unit
T
SETUP
4 µs
ADC Clock Frequency 700 KHz