Datasheet

103
A/T89C51AC2
4127H–8051–02/08
Figure 51. I
CC
Test Condition, Idle Mode
Figure 52. I
CC
Test Condition, Power-Down Mode
Figure 53. Clock Signal Waveform for I
CC
Tests in Active and Idle Modes
RST
EA
XTAL2
XTAL1
V
SS
V
CC
V
CC
I
CC
(NC)
P0
V
CC
All other pins are disconnected.
CLOCK
SIGNAL
RST
EA
XTAL2
XTAL1
V
SS
V
CC
V
CC
I
CC
(NC)
P0
V
CC
All other pins are disconnected.
V
CC
-0.5V
0.45V
0.7V
CC
0.2V
CC
-0.1
T
CLCH
T
CHCL
T
CLCH
= T
CHCL
= 5ns.