Datasheet

100
A/T89C51AC2
4127H–8051–02/08
Table 75. IPH1 Register
IPH1 (S:F7h)
Interrupt High Priority Register 1
Reset Value = XXXX X000b
7 6 5 4 3 2 1 0
- - - - - - PADCH -
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1 PADCH
ADC Interrupt Priority Level Most Significant bit
PADCH PADCL Priority level
0 0 Lowest
0 1
1 0
1 1 Highest
0 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.