Datasheet

4337K–USB–04/08

AT89C5130A/31A-M

19.3.3 Error Conditions

The following flags in the SPSTA signal SPI error conditions:

19.3.3.1 Mode Fault (MODF)

Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is

inconsistent with the actual mode of the device. MODF is set to warn that there may have a

multi-master conflict for system control. In this case, the SPI system is affected in the following

ways:

• An SPI receiver/error CPU interrupt request is generated,

• The SPEN bit in SPCON is cleared. This disable the SPI,

• The MSTR bit in SPCON is cleared

When SS

DISable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the

SS signal becomes “0”.

However, as stated before, for a system with one Master, if the SS pin of the Master device is

pulled low, there is no way that another Master attempt to drive the network. In this case, to pre-

vent the MODF flag from being set, software can set the SSDIS bit in the SPCON register and

therefore making the SS pin as a general-purpose I/O pin.

Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed

by a write to the SPCON register. SPEN Control bit may be restored to its original set state after

the MODF bit has been cleared.

19.3.3.2 Write Collision (WCOL)

A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done

during a transmit sequence.

WCOL does not cause an interruption, and the transfer continues uninterrupted.

Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an

access to SPDAT.

19.3.3.3 Overrun Condition

An overrun condition occurs when the Master device tries to send several data bytes and the

Slave devise has not cleared the SPIF bit issuing from the previous data byte transmitted. In this

case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read of the

SPDAT returns this byte. All others bytes are lost.

This condition is not detected by the SPI peripheral.

19.3.4 Interrupts

Two SPI status flags can generate a CPU interrupt requests:

Table 19-2. SPI Interrupts

Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been

completed. SPIF bit generates transmitter CPU interrupt requests.

Flag Request

SPIF (SP Data Transfer) SPI Transmitter Interrupt request

MODF (Mode Fault) SPI Receiver/Error Interrupt Request (if SSDIS = “0”)