Datasheet

95
4337K–USB–04/08
AT89C5130A/31A-M
19.3 Functional Description
Figure 19-2 shows a detailed structure of the SPI module.
Figure 19-2. SPI Module Block Diagram
19.3.1 Operating Modes
The Serial Peripheral Interface can be configured as one of the two modes: Master mode or
Slave mode. The configuration and initialization of the SPI module is made through one register:
• The Serial Peripheral CONtrol register (SPCON)
Once the SPI is configured, the data exchange is made using:
• SPCON
• The Serial Peripheral STAtus register (SPSTA)
• The Serial Peripheral DATa register (SPDAT)
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the
two serial data lines (MOSI and MISO). A Slave Select line (SS
) allows individual selection of a
Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities.
1 1 1 Don’t Use No BRG
SPR2 SPR1 SPR0 Clock Rate Baud Rate Divisor (BD)
Shift Register
01
234567
Internal Bus
Pin
Control
Logic
MISO
MOSI
SCK
M
S
Clock
Logic
Clock
Divider
Clock
Select
/4
/64
/128
SPI Interrupt Request
8-bit bus
1-bit signal
SS
FCLK PERIPH
/32
/8
/16
Receive Data Register
SPDAT
SPI
Control
SPSTA
CPHA
SPR0
SPR1
CPOLMSTRSSDISSPEN
SPR2
SPCON
WCOL MODFSPIF
- - - -
SSERR