Datasheet

33
4337K–USB–04/08
AT89C5130A/31A-M
Table 8-3. Programming Spaces
The Flash memory enters a busy state as soon as programming is launched. In this state, the
memory is not available for fetching code. Thus to avoid any erratic execution during program-
ming, the CPU enters Idle mode. Exit is automatically performed at the end of programming.
Note: Interrupts that may occur during programming time must be disabled to avoid any spurious exit of
the idle mode.
8.3.3 Status of the Flash Memory
The bit FBUSY in FCON register is used to indicate the status of programming.
FBUSY is set when programming is in progress.
8.3.4 Selecting FM0/FM1
The bit ENBOOT in AUXR1 register is used to choose between FM0 and FM1 mapped up to
F800h.
8.3.5 Loading the Column Latches
Any number of data from 1 byte to 128 bytes can be loaded in the column latches. This provides
the capability to program the whole memory by byte, by page or by any number of bytes in a
page.
When programming is launched, an automatic erase of the locations loaded in the column
latches is first performed, then programming is effectively done. Thus, no page or block erase is
needed and only the loaded data are programmed in the corresponding page.
The following procedure is used to load the column latches and is summarized in Figure 8-5:
• Map the column latch space by setting FPS bit.
• Load the DPTR with the address to load.
• Load Accumulator register with the data to load.
• Execute the MOVX @DPTR, A instruction.
• If needed loop the three last instructions until the page is completely loaded.
Write to FCON
OperationFPL3:0 FPS FMOD1 FMOD0
User
5 X 0 0 No action
A X 0 0
Write the column latches in user
space
Extra Row
5 X 0 1 No action
A X 0 1
Write the column latches in extra row
space
Security
Space
5 X 1 0 No action
A X 1 0 Write the fuse bits space
Reserved
5 X 1 1 No action
A X 1 1 No action