Datasheet

32
4337K–USB–04/08
AT89C5130A/31A-M
8.2.1.4 Column Latches
The column latches, also part of FM0, have a size of full page (128 bytes).
The column latches are the entrance buffers of the three previous memory locations (user array,
XRow and Hardware security byte).
8.3 Overview of FM0 Operations
The CPU interfaces to the Flash memory through the FCON register and AUXR1 register.
These registers are used to:
• Map the memory spaces in the adressable space
• Launch the programming of the memory spaces
• Get the status of the Flash memory (busy/not busy)
• Select the Flash memory FM0/FM1.
8.3.1 Mapping of the Memory Space
By default, the user space is accessed by MOVC instruction for read only. The column latches
space is made accessible by setting the FPS bit in FCON register. Writing is possible from
0000h to 3FFFH/7FFFh, address bits 6 to 0 are used to select an address within a page while
bits 14 to 7 are used to select the programming address of the page.
Setting this bit takes precedence on the EXTRAM bit in AUXR register.
The other memory spaces (user, extra row, hardware security) are made accessible in the code
segment by programming bits FMOD0 and FMOD1 in FCON register in accordance with
Table 8-2. A MOVC instruction is then used for reading these spaces.
Table 8-2. FM0 Blocks Select Bits
8.3.2 Launching Programming
FPL3:0 bits in FCON register are used to secure the launch of programming. A specific
sequence must be written in these bits to unlock the write protection and to launch the program-
ming. This sequence is 5 followed by A. Table 8-3 summarizes the memory spaces to program
according to FMOD1:0 bits.
FMOD1 FMOD0 FM0 Adressable Space
0 0 User (0000h-FFFFh)
0 1 Extra Row(FF80h-FFFFh)
1 0 Hardware Security (0000h)
1 1 reserved