Datasheet

31
4337K–USB–04/08
AT89C5130A/31A-M
8.2 Flash Memory Architecture
AT89C5130A/31A-M features two on-chip Flash memories:
• Flash memory FM0:
containing 32 Kbytes of program memory (user space) organized into 128-byte pages,
• Flash memory FM1:
3 Kbytes for bootloader and Application Programming Interfaces (API).
The FM0 supports both parallel programming and Serial In-System Programming (ISP) whereas
FM1 supports only parallel programming by programmers. The ISP mode is detailed in the “In-
System Programming” section.
All Read/Write access operations on Flash memory by user application are managed by a set of
API described in the “In-System Programming” section.
Figure 8-4. Flash Memory Architecture
8.2.1 FM0 Memory Architecture
The Flash memory is made up of 4 blocks (see Figure 8-4):
1. The memory array (user space) 32 Kbytes
2. The Extra Row
3. The Hardware security bits
4. The column latch registers
8.2.1.1 User Space
This space is composed of a 16/32 Kbytes Flash memory organized in 128/256 pages of 128
bytes. It contains the user’s application code.
8.2.1.2 Extra Row (XRow)
This row is a part of FM0 and has a size of 128 bytes. The extra row contains information for
bootloader usage (see
9-3 “Software Registers” on page 41)
8.2.1.3 Hardware Security Space
The hardware security space is a part of FM0 and has a size of 1 byte.
The 4 MSB can be read/written by software. The 4 LSB can only be read by software and written
by hardware in parallel mode.
7FFFh for
16/32 KB
Flash Memory
FM0
0000h
Hardware Security (1 Byte)
Column Latches (128 Bytes)
User Space
Extra Row (128 Bytes)
3 Kbytes
Flash Memory
FM1
Boot Space
FFFFh
F400h
FM1 mapped between FFFFh and
F400h when bit ENBOOT is set in
AUXR1 register
3FFFh for
AT89C5131A
for 32 KB
AT89C5130A
for 16 KB