Datasheet

30
4337K–USB–04/08
AT89C5130A/31A-M
Figure 8-2. External Code Memory Interface Structure
Table 8-1. External Data Memory Interface Signals
8.1.2 External Bus Cycles
This section describes the bus cycles the AT89C5130A/31A-M executes to fetch code (see
Figure 8-3) in the external program/code memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock peri-
ods in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2
mode (see the clock Section).
For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and
do not provide precise timing information.
Figure 8-3. External Code Fetch Waveforms
Signal
Name Type Description
Alternate
Function
A15:8 O
Address Lines
Upper address lines for the external bus.
P2.7:0
AD7:0 I/O
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
P0.7:0
ALE O
Address Latch Enable
ALE signals indicates that valid address information are available on lines
AD7:0.
-
PSEN O
Program Store Enable Output
This signal is active low during external code fetch or external code read
(MOVC instruction).
-
Flash
EPROM
AT89C5130A
AT89C5131
P2
P0
AD7:0
A15:8
A7:0
A15:8
D7:0
A7:0
ALE
Latch
OEPSEN
ALE
P0
P2
PSEN
PCL
PCHPCH
PCLD7:0 D7:0
PCH
D7:0
CPU Clock