Datasheet

174
4337K–USB–04/08
AT89C5130A/31A-M
V
DD
= 2.7 to 5.5 V, T
A
= -40 to +85°C
Note: T
PER
is XTAL period when SPI interface operates in X2 mode or twice XTAL period when SPI
interface operates in X1 mode.
Symbol Parameter Min Max Unit
Slave Mode
T
CHCH
Clock Period 2 T
PER
T
CHCX
Clock High Time 0.8 T
PER
T
CLCX
Clock Low Time 0.8 T
PER
T
SLCH
, T
SLCL
SS Low to Clock edge 100 ns
T
IVCL
, T
IVCH
Input Data Valid to Clock Edge 50 ns
T
CLIX
, T
CHIX
Input Data Hold after Clock Edge 50 ns
T
CLOV,
T
CHOV
Output Data Valid after Clock Edge 50 ns
T
CLOX
, T
CHOX
Output Data Hold Time after Clock Edge 0 ns
T
CLSH
, T
CHSH
SS High after Clock Edge 0 ns
T
SLOV
SS Low to Output Data Valid 4T
PER
+20 ns
T
SHOX
Output Data Hold after SS High 2T
PER
+100 ns
T
SHSL
SS High to SS Low 2T
PER
+120
T
ILIH
Input Rise Time 2 µ s
T
IHIL
Input Fall Time 2 µ s
T
OLOH
Output Rise time 100 ns
T
OHOL
Output Fall Time 100 ns
Master Mode
T
CHCH
Clock Period 4 T
PER
T
CHCX
Clock High Time 2T
PER
-20 ns
T
CLCX
Clock Low Time 2T
PER
-20 ns
T
IVCL
, T
IVCH
Input Data Valid to Clock Edge 50 ns
T
CLIX
, T
CHIX
Input Data Hold after Clock Edge 50 ns
T
CLOV,
T
CHOV
Output Data Valid after Clock Edge 20 ns
T
CLOX
, T
CHOX
Output Data Hold Time after Clock Edge 0 ns