Datasheet

17
4337K–USB–04/08
AT89C5130A/31A-M
5.4 Registers
Table 5-2. CKCON0 (S:8Fh)
Clock Control Register 0
32 MHz 3 2 21h
40 MHz 12 10 B9h
Oscillator Frequency R+1 N+1 PLLDIV
7 6 5 4 3 2 1 0
TWIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2
Bit Number
Bit
Mnemonic Description
7 TWIX2
TWI Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
6 WDX2
Watchdog Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
5 PCAX2
Programmable Counter Array Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
4 SIX2
Enhanced UART Clock (Mode 0 and 2)
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
3 T2X2
Timer2 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
2 T1X2
Timer1 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
1 T0X2
Timer0 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
0 X2
System Clock Control bit
Clear to select 12 clock periods per machine cycle (STD mode, F
CPU
= F
PER =
F
OSC
/ 2).
Set to select 6 clock periods per machine cycle (X2 mode, F
CPU =
F
PER =
F
OSC
).