Datasheet

137
4337K–USB–04/08
AT89C5130A/31A-M
21.10.2 USB Interrupt Control System
As shown in Figure 21-16, many events can produce a USB interrupt:
• TXCMPL: Transmitted In Data (see Table 21-9 on page 144). This bit is set by hardware
when the Host accept a In packet.
• RXOUTB0: Received Out Data Bank 0 (see Table 21-9 on page 144). This bit is set by
hardware when an Out packet is accepted by the endpoint and stored in bank 0.
• RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (see
Table 21-9 on
page 144). This bit is set by hardware when an Out packet is accepted by the endpoint and
stored in bank 1.
• RXSETUP: Received Setup (see Table 21-9 on page 144). This bit is set by hardware when
an SETUP packet is accepted by the endpoint.
• STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (see Table 21-9 on page
144). This bit is set by hardware when a STALL handshake has been sent as requested by
STALLRQ, and is reset by hardware when a SETUP packet is received.
• SOFINT: Start of Frame Interrupt (See “USBIEN Register USBIEN (S:BEh) USB Global
Interrupt Enable Register” on page 141.). This bit is set by hardware when a USB Start of
Frame packet has been received.
• WUPCPU: Wake-Up CPU Interrupt (See “USBIEN Register USBIEN (S:BEh) USB Global
Interrupt Enable Register” on page 141.). This bit is set by hardware when a USB resume is
detected on the USB bus, after a SUSPEND state.
• SPINT: Suspend Interrupt (See “USBIEN Register USBIEN (S:BEh) USB Global Interrupt
Enable Register” on page 141.). This bit is set by hardware when a USB suspend is detected
on the USB bus.