Datasheet

122
4337K–USB–04/08
AT89C5130A/31A-M
Figure 21-3. UFI Block Diagram
Figure 21-4. Minimum Intervention from the USB Device Firmware
21.2 Configuration
21.2.1 General Configuration
• USB controller enable
Before any USB transaction, the 48 MHz required by the USB controller must be correctly
generated (See “Clock Controller” on page 14.).
The USB controller will be then enabled by setting the EUSB bit in the USBCON register.
• Set address
After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit in the
USBADDR register. This action will allow the USB controller to answer to the requests sent
at the address 0.
When a SET_ADDRESS request has been received, the USB controller must only answer
to the address defined by the request. The new address will be stored in the USBADDR reg-
ister. The FEN bit and the FADDEN bit in the USBCON register will be set to allow the USB
controller to answer only to requests sent at the new address.
Transfer
Control
FSM
DPR Control
USB Side
CSREG 0 to 7
Registers
Bank
DPR Control
mP side
FIU
User DPRAM
Up to 48 MHz
UC_sysclk
C51
Microcontroller
Interface
Asynchronous Information
Transfer
Endpoint 0
Endpoint 1
Endpoint 2
Endpoint 3
SIE
DPLL
Endpoint 4
Endpoint 5
Endpoint 6
OUT Transactions:
HOST
UFI
C51
OUT DATA0 (n bytes)
ACK
Endpoint FIFO read (n bytes)
OUT DATA1
NACK
OUT DATA1
ACK
IN Transactions:
HOST
UFI
C51
IN
ACK
Endpoint FIFO write
IN
DATA1
NACK
interrupt C51
IN
DATA1
interrupt C51
Endpoint FIFO write