Datasheet

118
4337K–USB–04/08
AT89C5130A/31A-M
20.3 Registers
Table 20-10. SSCON Register
SSCON - Synchronous Serial Control Register (93h)
7 6 5 4 3 2 1 0
CR2 SSIE STA STO SI AA CR1 CR0
Bit Number
Bit
Mnemonic Description
7 CR2
Control Rate bit 2
See .
6 SSIE
Synchronous Serial Interface Enable bit
Clear to disable SSLC.
Set to enable SSLC.
5 STA
Start flag
Set to send a START condition on the bus.
4 ST0
Stop flag
Set to send a STOP condition on the bus.
3 SI
Synchronous Serial Interrupt flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
2 AA
Assert Acknowledge flag
Clear in master and slave receiver modes, to force a not acknowledge (high level on
SDA).
Clear to disable SLA or GCA recognition.
Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter
modes.
Set in master and slave receiver modes, to force an acknowledge (low level on SDA).
This bit has no effect when in master transmitter mode.
1 CR1
Control Rate bit 1
See Table 20-4
0 CR0
Control Rate bit 0
See Table 20-4
Table 20-11. SSDAT (095h) - Synchronous Serial Data Register (read/write)
SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
7 6 5 4 3 2 1 0
Bit Number
Bit
Mnemonic Description
7 SD7 Address bit 7 or Data bit 7.
6 SD6 Address bit 6 or Data bit 6.
5 SD5 Address bit 5 or Data bit 5.
4 SD4 Address bit 4 or Data bit 4.
3 SD3 Address bit 3 or Data bit 3.
2 SD2 Address bit 2 or Data bit 2.