Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 (10x10) 8-Bit 48 MHz I/O number 34

Features

• 80C52X2 Core (6 Clocks per Instruction)

– Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode

– Dual Data Pointer

– Full-duplex Enhanced UART (EUART)

– Three 16-bit Timer/Counters: T0, T1 and T2

– 256 Bytes of Scratchpad RAM

• 16/32-Kbyte On-chip Flash EEPROM In-System Programming through USB

– Byte and Page (128 bytes) Erase and Write

– 100k Write Cycles

• 3-KbyteFlash EEPROM for Bootloader

– Byte and Page (128 bytes) Erase and Write

– 100k Write Cycles

• 1-Kbyte EEPROM Data (

– Byte and Page (128 bytes) Erase and Write

– 100k Write Cycles

• On-chip Expanded RAM (ERAM): 1024 Bytes

• Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply

• USB 1.1 and 2.0 Full Speed Compliant Module with Interrupt on Transfer Completion

– Endpoint 0 for Control Transfers: 32-byte FIFO

– 6 Programmable Endpoints with In or Out Directions and with Bulk, Interrupt or

Isochronous Transfers

• Endpoint 1, 2, 3: 32-byte FIFO

• Endpoint 4, 5: 2 x 64-byte FIFO with Double Buffering (Ping-pong Mode)

• Endpoint 6: 2 x 512-byte FIFO with Double Buffering (Ping-pong Mode)

– Suspend/Resume Interrupts

– 48 MHz PLL for Full-speed Bus Operation

– Bus Disconnection on Microcontroller Request

• 5 Channels Programmable Counter Array (PCA) with 16-bit Counter, High-speed

Output, Compare/Capture, PWM and Watchdog Timer Capabilities

• Programmable Hardware Watchdog Timer (One-time Enabled with Reset-out): 100 ms

to 3s at 8 MHz

• Keyboard Interrupt Interface on Port P1 (8 Bits)

• TWI (Two Wire Interface) 400Kbit/s

• SPI Interface (Master/Slave Mode)

• 34 I/O Pins

• 4 Direct-drive LED Outputs with Programmable Current Sources: 2-6-10 mA Typical

• 4-level Priority Interrupt System (11 sources)

• Idle and Power-down Modes

• 0 to 24 MHz On-chip Oscillator with Analog PLL for 48 MHz Synthesis

• Industrial Temperature Range

• Extended Range Power Supply: 2.7V to 5.5V (3.3V to 5.5V required for USB)

• Packages: PLCC52, VQFP64, QFN32

8-bit Flash

Microcontroller

with Full Speed

USB Device

AT89C5130A-M

AT89C5131A-M

Summary of content (188 pages)

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Features • 80C52X2 Core (6 Clocks per Instruction) • • • • • • • • • • • • • • • • • • • – Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode – Dual Data Pointer – Full-duplex Enhanced UART (EUART) – Three 16-bit Timer/Counters: T0, T1 and T2 – 256 Bytes of Scratchpad RAM 16/32-Kbyte On-chip Flash EEPROM In-System Programming through USB – Byte and Page (128 bytes) Erase and Write – 100k Write Cycles 3-KbyteFlash EEPROM for Bootloader – Byte and Page (128 bytes) Erase and Write – 100k Write C
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1. Description AT89C5130A/31A-M is a high-performance Flash version of the 80C51 single-chip 8-bit microcontrollers with full speed USB functions. AT89C5130A/31A-M features a full-speed USB module compatible with the USB specifications Version 1.1 and 2.0. This module integrates the USB transceivers with a 3.3V voltage regulator and the Serial Interface Engine (SIE) with Digital Phase Locked Loop and 48 MHz clock recovery.
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AT89C5130A/31A-M XTAL1 XTAL2 EUART + BRG ALE RAM 256x8 EEPROM ERAM 4Kx8 1Kx8 16/32Kx8Flash (1) (1) PCA Timer2 SCK MISO MOSI SDA SCL T2 T2EX CEX ECI VDD VSS TxD (1) (1) (2) (2) SS RxD 2. Block Diagram (1) (1) (1) (1) (3) (3) SPI TWI C51 CORE PSEN CPU EA Notes: D+ D- KIN [0..7] P4 P3 P2 P1 P0 INT1 (2) (2) Regulator VREF AVDD Key Watch USB Board Dog AVSS Parallel I/O Ports & Ext.
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3. Pinout Description Pinout 1 52 51 50 49 48 47 4 P1.0/T2/KIN0 P2.0/A8 2 P1.2/ECI/KIN2 P2.1/A9 3 P1.1/T2EX/KIN1/SS P2.2/A10 5 4 P1.3/CEX0/KIN3 P1.6/CEX3/KIN6/SCK P1.5/CEX2/KIN5/MISO 6 P1.4/CEX1/KIN4 P1.7/CEX4/KIN7/MOSI 7 P0.0/AD0 P4.0/SCL AT89C5130A/31A-M 52-pin PLCC Pinout P4.1/SDA 8 46 NC P2.3/A11 9 45 P0.1/AD1 P2.4/A12 10 44 P0.2/AD2 P2.5/A13 11 43 XTAL2 12 42 RST P0.3/AD3 XTAL1 13 P2.6/A14 P2.7/A15 14 VDD AVDD 41 VSS P0.4/AD4 15 40 39 16 38 P0.
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AT89C5130A/31A-M NC P1.1/T2EX/KIN1/SS P1.0/T2/KIN0 P1.2/ECI/KIN2 P1.3/CEX0/KIN3 P0.0/AD0 P1.4/CEX1/KIN4 P2.1/A9 P2.0/A8 P2.2/A10 P1.5/CEX2/KIN5/MISO P1.6/CEX3/KIN6/SCK NC AT89C5130A/31A-M 64-pin VQFP Pinout P4.1/SDA P4.0/SCL P1.7/CEX4/KIN7/MOSI Figure 3-2. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC P2.3/A11 1 2 48 47 NC P2.4/A12 3 46 P0.1/AD1 P2.5/A13 4 45 P0.2/AD2 XTAL2 XTAL1 5 6 44 43 RST P0.3/AD3 VSS P2.6/A14 7 42 P2.7/A15 VDD AVDD 8 9 41 40 UCAP AVSS NC P3.
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P1.2/ECI/KIN2 P1.1/T2EX/KIN1/SS P1.3/CEX0/KIN3 P1.5/CEX2/KIN5/MISO P1.4/CEX1/KIN4 P1.7/CEX4/KIN7/MOSI P1.6/CEX3/KIN6/SCK AT89C5130A/31A-M 32-pin QFN Pinout P4.0/SCL Figure 3-3. 32 31 30 29 28 27 26 25 P4.1/SDA 1 24 P1.0/T2/KIN0 XTAL2 2 23 RST XTAL1 3 22 NC VDD 4 21 VSS UCAP 5 20 NC AVSS 6 19 P3.7/RD/LED3 P3.0/RxD 7 18 P3.6/WR/LED2 PLLF 8 17 P3.5/T1/LED1 QFN32 P3.4/T0 P3.2/INT0 P3.3/INT1/LED0 UVSS P3.
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AT89C5130A/31A-M Signal Name Type Description Capture External Input CEX[4:0] I/O Compare External Output Alternate Function P1.3 P1.4 P1.5 P1.6 P1.7 Table 3-3. Serial I/O Signal Description Signal Name Type RxD I Serial Input Port P3.0 TxD O Serial Output Port P3.1 Table 3-4.
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Table 3-5. LED Signal Description Signal Name LED[3:0] Table 3-6. Type O Alternate Function Description Direct Drive LED Output These pins can be directly connected to the Cathode of standard LEDs without external current limiting resistors. The typical current of each output can be programmed by software to 2, 6 or 10 mA. Several outputs can be connected together to get higher drive capabilities. P3.3 P3.5 P3.6 P3.
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AT89C5130A/31A-M Table 3-8. Ports Signal Description Signal Name P0[7:0] P1[7:0] Type I/O I/O Description Port 0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, Floating P0 inputs must be pulled to VDD or VSS. Port 1 P1 is an 8-bit bidirectional I/O port with internal pull-ups.
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Table 3-10. USB Signal Description Signal Name Type D+ I/O D- I/O VREF O Table 3-11. Alternate Function Description USB Data + signal - Set to high level under reset. USB Data - signal - Set to low level under reset. USB Reference Voltage Connect this pin to D+ using a 1.5 kΩ resistor to use the Detach function.
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AT89C5130A/31A-M Table 3-12. Power Signal Description (Continued) Signal Name Type Description AVDD PWR Analog Supply Voltage AVDD is used to supply the on-chip PLL and the USB PAD. - VSS GND Digital Ground VSS is used to supply the buffer ring and the digital core. - UVSS GND USB Digital Ground UVSS is used to supply the USB pads.
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4. Typical Application 4.1 Recommended External components All the external components described in the figure below must be implemented as close as possible from the microcontroller package. The following figure represents the typical wiring schematic. Figure 4-1. Typical Application VDD 100nF VSS VSS AVDD 1.5K VSS VDD VDD USB 100nF 4.7µF VRef AT89C5130A/31A-M VBUS 27R D+ 27R DGND D+ DUVSS VSS XTAL1 22pF UCAP Q 1µF 22pF +20% VSS 100R 2.
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AT89C5130A/31A-M 4.2 PCB Recommandations Figure 4-2. USB Pads Components must be close to the microcontroller Wires must be routed in Parallel and must be as short as possible VRef D+ D- USB Connector If possible, isolate D+ and D- signals from other signals with ground wires Figure 4-3.
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5. Clock Controller 5.1 Introduction The AT89C5130A/31A-M clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are generated by this controller. The AT89C5130A/31A-M X1 and X2 pins are the input and the output of a single-stage on-chip inverter (see Figure 5-1) that can be configured with off-chip components as a Pierce oscillator (see Figure 5-2).
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AT89C5130A/31A-M In order to optimize the power consumption, the oscillator inverter is inactive when the PLL output is not selected for the USB device. Figure 5-2. Crystal Connection X1 C1 Q C2 VSS 5.3 5.3.1 X2 PLL PLL Description The AT89C5130A/31A-M PLL is used to generate internal high frequency clock (the USB Clock) synchronized with an external low-frequency (the Peripheral Clock). The PLL clock is used to generate the USB interface clock. Figure 5-3 shows the internal structure of the PLL.
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Figure 5-4. PLL Filter Connection PLLF R C2 C1 VSS VSS The typical values are: R = 100 Ω, C1 = 10 nf, C2 = 2.2 nF. 5.3.2 PLL Programming The PLL is programmed using the flow shown in Figure 5-5. As soon as clock generation is enabled user must wait until the lock indicator is set to ensure the clock output is stable. Figure 5-5. PLL Programming Flow PLL Programming Configure Dividers N3:0 = xxxxb R3:0 = xxxxb Enable PLL PLLEN = 1 PLL Locked? LOCK = 1? 5.3.
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AT89C5130A/31A-M 5.4 Oscillator Frequency R+1 N+1 PLLDIV 32 MHz 3 2 21h 40 MHz 12 10 B9h Registers Table 5-2. CKCON0 (S:8Fh) Clock Control Register 0 7 6 5 4 3 2 1 0 TWIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Bit Number Mnemonic Description 7 6 5 4 3 2 1 0 TWIX2 TWI Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect. Clear to select 6 clock periods per peripheral clock cycle.
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Reset Value = 0000 0000b Table 5-3. CKCON1 (S:AFh) Clock Control Register 1 7 6 5 4 3 2 1 0 - - - - - - - SPIX2 Bit Bit Number Mnemonic Description 7-1 - 0 SPIX2 Reserved The value read from this bit is always 0. Do not set this bit. SPI Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, this bit has no effect. Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.
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AT89C5130A/31A-M Bit Bit Number Mnemonic Description 7-4 R3:0 PLL R Divider Bits 3-0 N3:0 PLL N Divider Bits Reset Value = 0000 0000 19 4337K–USB–04/08
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6.
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AT89C5130A/31A-M The table below shows all SFRs with their address and their reset value. Table 6-1.
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The Special Function Registers (SFRs) of the AT89C5131 fall into the following categories: Table 6-2. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h DPL 82h 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Stack Pointer LSB of SPX Data Pointer Low byte LSB of DPTR DPH 83h Data Pointer High byte MSB of DPTR Table 6-3. Table 6-4.
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AT89C5130A/31A-M Table 6-4. Timer SFR’s (Continued) Mnemonic Add Name RCAP2H CBh Timer/Counter 2 Reload/Capture High byte RCAP2L CAh Timer/Counter 2 Reload/Capture Low byte WDTRST A6h WatchDog Timer Reset WDTPRG A7h WatchDog Timer Program Table 6-5.
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Table 6-7.
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AT89C5130A/31A-M Table 6-10. Keyboard SFRs Mnemonic Add Name KBLS 9Ch Keyboard Level Selector Register Table 6-11.
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Table 6-13. USB SFR’s Mnemonic Add Name 7 6 5 4 3 2 1 0 UBYCTLX E2h USB Byte Counter Low (EP X) BYCT7 BYCT6 BYCT5 BYCT4 BYCT3 BYCT2 BYCT1 BYCT0 UBYCTHX E3h USB Byte Counter High (EP X) - - - - - BYCT10 BYCT9 BYCT8 UFNUML BAh USB Frame Number Low FNUM7 FNUM6 FNUM5 FNUM4 FNUM3 FNUM2 FNUM1 FNUM0 UFNUMH BBh USB Frame Number High - - CRCOK CRCERR - FNUM10 FNUM9 FNUM8 Table 6-14.
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AT89C5130A/31A-M 7. Dual Data Pointer Register The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 7-1) that allows the program code to switch between them (see Figure 7-1). Figure 7-1.
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ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data poin
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AT89C5130A/31A-M 8. Program/Code Memory The AT89C5130A/31A-M implement 16/ 32 Kbytes of on-chip program/code memory. Figure 81 shows the split of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD voltage.
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Figure 8-2. External Code Memory Interface Structure Flash EPROM AT89C5130A AT89C5131 A15:8 P2 A15:8 ALE P0 AD7:0 Latch A7:0 A7:0 D7:0 PSEN Table 8-1. 8.1.2 OE External Data Memory Interface Signals Signal Name Type Alternate Function A15:8 O Address Lines Upper address lines for the external bus. P2.7:0 AD7:0 I/O Address/Data Lines Multiplexed lower address lines and data for the external memory. P0.
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AT89C5130A/31A-M 8.2 Flash Memory Architecture AT89C5130A/31A-M features two on-chip Flash memories: • Flash memory FM0: containing 32 Kbytes of program memory (user space) organized into 128-byte pages, • Flash memory FM1: 3 Kbytes for bootloader and Application Programming Interfaces (API). The FM0 supports both parallel programming and Serial In-System Programming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP mode is detailed in the “InSystem Programming” section.
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8.2.1.4 8.3 Column Latches The column latches, also part of FM0, have a size of full page (128 bytes). The column latches are the entrance buffers of the three previous memory locations (user array, XRow and Hardware security byte). Overview of FM0 Operations The CPU interfaces to the Flash memory through the FCON register and AUXR1 register.
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AT89C5130A/31A-M Table 8-3. Programming Spaces Write to FCON FPL3:0 FPS FMOD1 FMOD0 Operation 5 X 0 0 No action A X 0 0 Write the column latches in user space 5 X 0 1 No action A X 0 1 Write the column latches in extra row space 5 X 1 0 No action A X 1 0 Write the fuse bits space 5 X 1 1 No action A X 1 1 No action User Extra Row Security Space Reserved The Flash memory enters a busy state as soon as programming is launched.
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Figure 8-5. Column Latches Loading Procedure Column Latches Loading Column Latches Mapping FPS = 1 Data Load DPTR = Address ACC = Data Exec: MOVX @DPTR, A Last Byte to load? Data memory Mapping FPS = 0 8.3.6 8.3.6.1 Programming the Flash Spaces User The following procedure is used to program the User space and is summarized in Figure 8-6: • Load data in the column latches from address 0000h to 7FFFh(1). • Disable the interrupts.
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AT89C5130A/31A-M Figure 8-6. Flash and Extra Row Programming Procedure Flash Spaces Programming Column Latches Loading see Figure 8-5 Disable IT EA = 0 Launch Programming FCON = 5xh FCON = Axh FBusy Cleared? Erase Mode FCON = 00h End Programming Enable IT EA = 1 8.3.6.3 Hardware Security The following procedure is used to program the Hardware Security space and is summarized in Figure 8-7: • Set FPS and map Hardware byte (FCON = 0x0C) • Disable the interrupts. • Load DPTR at address 0000h.
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Figure 8-7. Hardware Programming Procedure Flash Spaces Programming FCON = 0Ch Data Load DPTR = 00h ACC = Data Exec: MOVX @DPTR, A Disable IT EA = 0 Launch Programming FCON = 54h FCON = A4h FBusy Cleared? Erase Mode FCON = 00h End Programming Enable IT EA = 1 8.3.7 8.3.7.1 Reading the Flash Spaces User The following procedure is used to read the User space and is summarized in Figure 8-8: • Map the User space by writing 00h in FCON register.
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AT89C5130A/31A-M 8.3.7.3 Hardware Security The following procedure is used to read the Hardware Security space and is summarized in Figure 8-8: • Map the Hardware Security space by writing 04h in FCON register. • Read the byte in Accumulator by executing MOVC A, @A+DPTR with A = 0 & DPTR = 0000h. Figure 8-8. Reading Procedure Flash Spaces Reading Flash Spaces Mapping FCON = 00000xx0b Data Read DPTR = Address ACC = 0 Exec: MOVC A, @A+DPTR Erase Mode FCON = 00h 8.4 Registers Table 8-4.
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9. Flash EEPROM Memory 9.1 General Description The Flash memory increases EPROM functionality with in-circuit electrical erasure and programming. It contains 16/32 Kbytes of program memory organized in 128/256 pages of 128 bytes, respectively. This memory is both parallel and serial In-System Programmable (ISP). ISP allows devices to alter their own program memory in the actual end product under software control. A default serial loader (bootloader) program allows ISP of the Flash.
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AT89C5130A/31A-M 9.4 Flash Registers and Memory Map The AT89C5130A/31A-M Flash memory uses several registers: • Hardware register can be accessed with a parallel programmer.Some bits of the hardware register can be changed, also, by API (i.e. X2 and BLJB bits of Hardware security Byte) or ISP. • Software registers are in a special page of the Flash memory which can be accessed through the API or with the parallel programming modes.
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Table 9-2. Program Lock bits Program Lock Bits Notes: Security level LB0 LB1 LB2 Protection Description 1 U U U No program lock features enabled. 2 P U U MOVC instruction executed from external program memory is disabled from fetching code bytes from any internal memory, EA is sampled and latched on reset, and further parallel programming of the Flash and of the EEPROM (boot and Xdata) is disabled. ISP and software programming with API are still allowed.
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AT89C5130A/31A-M Table 9-3.
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Table 9-5. Program Lock Bits of the SSB Program Lock Bits Notes: Security Level LB0 LB1 1 U U No program lock features enabled. 2 P U ISP programming of the Flash is disabled. 3 P P Same as 2, also verify through ISP programming interface is disabled. Protection Description 1. U: unprogrammed or "one" level. 2. P: programmed or “zero” level. 3. WARNING: Security level 2 and 3 should only be programmed after Flash and code verification. 9.
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AT89C5130A/31A-M 10. EEPROM Data Memory 10.1 Description The 1-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 03FFh of the ERAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming).
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10.5 Registers Table 10-1. EECON (S:0D2h) EECON Register 7 6 5 4 3 2 1 0 EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY Bit Number Bit Mnemonic 7-4 EEPL3-0 Programming Launch command bits Write 5Xh followed by AXh to EEPL to launch the programming. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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AT89C5130A/31A-M 11. In-System Programming (ISP) With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the AT89C5130A/31A-M allows the system engineer the development of applications with a very high level of flexibility. This flexibility is based on the possibility to alter the customer program at any stages of a product’s life: • Before mounting the chip on the PCB, FM0 flash can be programmed with the application code.
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Figure 11-1. Flash Memory Mapping FFFFh F400h 3FFFh 7FFFh Custom Bootloader [SBV]00h Custom Bootloader 32K Bytes Flash Memory Flash Memory FM0 0000h FM0 0000h C5130A 11.2.1 FM1 Mapped between F400h and FFFFh when API Called [SBV]00h 16K Bytes 11.2 3K Bytes IAP Bootloader FM1 C5131A Boot Process Software Boot Process Example Many algorithms can be used for the software boot process. Below are descriptions of the different flags and Bytes.
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AT89C5130A/31A-M Figure 11-2. Hardware Boot Process Algorithm bit ENBOOT in AUXR1 Register Is Initialized with BLJB Inverted. RESET Hardware Example, if BLJB=0, ENBOOT is set (=1) during reset, thus the bootloader is executed after the reset. ENBOOT = 0 PC = 0000h BLJB == 0 ? Software ENBOOT = 1 PC = F400h 11.
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Description Copy of the Device ID#3: Name and Revision 11.5 Default Value Address FFh 61h Hardware Conditions It is possible to force the controller to execute the bootloader after a Reset with hardware conditions. Depending on the product type (low pin count or high pin count package), there are two methods to apply the hardware conditions. 11.5.
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AT89C5130A/31A-M Figure 11-4. Hardware conditions typical sequence during power-on. VCC PSEN RST 11.5.2 Low Pin Count Hardware Conditions (QFN32) Low pin count products do not have PSEN signal, thus for these products, the bootloader is always executed after reset thanks to the BLJB bit. The Hardware Condition are detected at the begining of the bootloader execution from reset. The default factory Hardware Condition is assigned to port P1.
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12. On-chip Expanded RAM (ERAM) The AT89C5130A/31A-M provides additional Bytes of random access memory (RAM) space for increased data parameters handling and high level language usage. AT89C5130A/31A-M devices have expanded RAM in external data space; maximum size and location are described in Table 12-1. Table 12-1.
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AT89C5130A/31A-M • Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2). • Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV atR0, # data where R0 contains 0A0h, accesses the data byte at address 0A0h, rather than P2 (whose address is 0A0h). • The ERAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions.
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Bit Bit Number Mnemonic Description Pulse length 5 M0 Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods (default). Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods. 4 - 3 XRS1 2 1 XRS0 EXTRAM Reserved The value read from this bit is indeterminate.
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AT89C5130A/31A-M 13. Timer 2 The Timer 2 in the AT89C5130A/31A-M is the standard C52 Timer 2. It is a 16-bit timer/counter: the count is maintained by two cascaded eight-bit timer registers, TH2 and TL2. It is controlled by T2CON (Table 13-1) and T2MOD (Table 13-2) registers. Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.
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Figure 13-1. Auto-reload Mode Up/Down Counter (DCEN = 1) FCLK PERIPH :6 0 1 T2 C/T2 TR2 T2CON T2CON (DOWN COUNTING RELOAD VALUE) T2EX: FFh (8-bit) FFh (8-bit) if DCEN = 1, 1 = UP if DCEN = 1, 0 = DOWN if DCEN = 0, up counting TOGGLE T2CON EXF2 TL2 (8-bit) TH2 (8-bit) TF2 T2CON RCAP2L (8-bit) Timer 2 INTERRUPT RCAP2H (8-bit) (UP COUNTING RELOAD VALUE) 13.2 Programmable Clock Output In the Clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 13-2).
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AT89C5130A/31A-M It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. Figure 13-2.
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Table 13-1. T2CON Register T2CON - Timer 2 Control Register (C8h) 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Bit Number Mnemonic 7 TF2 Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2 = 1.
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AT89C5130A/31A-M Table 13-2. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h) 7 6 5 4 3 2 1 0 - - - - - - T2OE DCEN Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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14. Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules.
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AT89C5130A/31A-M Figure 14-1. PCA Timer/Counter To PCA modules FCLK PERIPH/6 overflow FCLK PERIPH/2 CH T0 OVF It CL 16 Bit Up Counter P1.2 CIDL WDTE CF CR CPS1 CPS0 ECF CMOD 0xD9 CCF2 CCF1 CCF0 CCON 0xD8 Idle Table 14-1.
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Reset Value = 00XX X000b Not bit addressable The CMOD register includes three additional bits associated with the PCA (See Figure 14-1 and Table 14-1). • The CIDL bit allows the PCA to stop during idle mode. • The WDTE bit enables or disables the watchdog function on module 4. • The ECF bit when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows.
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AT89C5130A/31A-M Bit Bit Number Mnemonic 1 CCF1 0 CCF0 Description PCA Module 1 Interrupt Flag Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 0 Interrupt Flag Must be cleared by software. Set by hardware when a match or capture occurs. Reset Value = 000X 0000b Not bit addressable The watchdog timer function is implemented in module 4 (See Figure 14-4). The PCA interrupt system is shown in Figure 14-2. Figure 14-2.
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• The ECCF bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. • PWM (CCAPMn.1) enables the pulse width modulation mode. • The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module's capture/compare register. • The match bit MAT (CCAPMn.
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AT89C5130A/31A-M Bit Bit Number Mnemonic 1 PWMn Description Pulse Width Modulation Mode Cleared to disable the CEXn pin to be used as a pulse width modulated output. Set to enable the CEXn pin to be used as a pulse width modulated output. Enable CCF Interrupt 0 ECCFn Cleared to disable compare/capture flag CCFn in the CCON register to generate an interrupt. Set to enable compare/capture flag CCFn in the CCON register to generate an interrupt.
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Reset Value = XXXX XXXXb Not bit addressable Table 14-6.
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AT89C5130A/31A-M 14.1 PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH).
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Figure 14-4. PCA Compare Mode and PCA Watchdog Timer CCON CF Write to CCAPnL CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8 Reset PCA IT Write to CCAPnH 1 CCAPnH 0 CCAPnL Enable Match 16-bit Comparator CH RESET(1) CL PCA Counter/Timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CIDL Note: WDTE CPS1 CPS0 ECF CCAPMn, n = 0 to 4 0xDA to 0xDE CMOD 0xD9 1. Only for Module 4 Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen.
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AT89C5130A/31A-M Figure 14-5. PCA High-speed Output Mode CCON CF CR CCF4 CCF3 CCF2 CCF1 CCF0 0xD8 Write to CCAPnL Reset PCA IT Write to CCAPnH 1 CCAPnH 0 CCAPnL Enable 16-bit Comparator CH Match CL CEXn PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 0xDA to 0xDE Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen.
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Figure 14-6. PCA PWM Mode CCAPnH Overflow CCAPnL “0” Enable 8-bit Comparator CEXn < ≥ “1” CL PCA Counter/Timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 0xDA to 0xDE 14.5 PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge.
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AT89C5130A/31A-M 15. Serial I/O Port The serial I/O port in the AT89C5130A/31A-M is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates.
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Figure 15-3. UART Timings in Modes 2 and 3 RXD D0 Start Bit D1 D2 D3 D4 Data Byte D5 D6 D7 D8 Ninth Stop Bit Bit RI SMOD0 = 0 RI SMOD0 = 1 FE SMOD0 = 1 15.2 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).
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AT89C5130A/31A-M Slave C:SADDR1111 0011b SADEN1111 1101b Given1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit.
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SADEN - Slave Address Mask Register (B9h) 7 6 5 4 3 2 1 0 4 3 2 1 0 Reset Value = 0000 0000b Not bit addressable SADDR - Slave Address Register (A9h) 7 6 5 Reset Value = 0000 0000b Not bit addressable 15.3 Baud Rate Selection for UART for Mode 1 and 3 The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. Figure 15-4.
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AT89C5130A/31A-M 15.3.1 15.3.
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Bit Bit Number Mnemonic FE Description Framing Error bit (SMOD0 = 1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit 7 SM0 Serial port Mode bit 0 Refer to SM1 for serial port mode selection.
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AT89C5130A/31A-M Example of computed value when X2 = 1, SMOD1 = 1, SPD = 1 FOSC = 16.384 MHz Baud Rates FOSC = 24 MHz BRL Error (%) BRL Error (%) 115200 247 1.23 243 0.16 57600 238 1.23 230 0.16 38400 229 1.23 217 0.16 28800 220 1.23 204 0.16 19200 203 0.63 178 0.16 9600 149 0.31 100 0.16 4800 43 1.23 - - Example of computed value when X2 = 0, SMOD1 = 0, SPD = 0 FOSC = 16.384 MHz FOSC = 24 MHz Baud Rates BRL Error (%) BRL Error (%) 4800 247 1.23 243 0.
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BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah) 7 6 5 4 3 2 1 0 – – – – – – – – Reset Value = 0000 0000b Table 15-2. T2CON Register T2CON - Timer 2 Control Register (C8h) 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Bit Number Mnemonic 7 TF2 Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.
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AT89C5130A/31A-M Table 15-3. PCON Register PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Bit Number Mnemonic 7 SMOD1 6 SMOD0 5 - Description Serial port Mode bit 1 for UART Set to select double baud rate in mode 1, 2 or 3. Serial port Mode bit 0 for UART Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register. Reserved The value read from this bit is indeterminate. Do not set this bit.
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Bit Number Bit Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit 6 - Reserved The value read from this bit is indeterminate. Do not set this bit 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 BRR Baud Rate Run Control bit Cleared to stop the internal Baud Rate Generator. Set to start the internal Baud Rate Generator.
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AT89C5130A/31A-M 16. Interrupt System 16.1 Overview The AT89C5130A/31A-M has a total of 11 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt, USB interrupt and the PCA global interrupt. These interrupts are shown in Figure 16-1. Figure 16-1. Interrupt Control System High priority interrupt IPH, IPL TCON.0 IT0 3 INT0 IE0 0 3 TF0 TCON.
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Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (Table 16-3.) and in the Interrupt Priority High register (Table 16-4). Table 16-1. shows the bit values and priority levels associated with each combination. 16.2 Registers The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at address 004BH and Keyboard interrupt vector is located at address 003BH.
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AT89C5130A/31A-M Bit Bit Number Mnemonic 7 EA 6 EC Description Enable All interrupt bit Cleared to disable all interrupts. Set to enable all interrupts. PCA interrupt enable bit Cleared to disable. Set to enable. 5 ET2 Timer 2 overflow interrupt Enable bit Cleared to disable Timer 2 overflow interrupt. Set to enable Timer 2 overflow interrupt. 4 ES Serial port Enable bit Cleared to disable serial port interrupt. Set to enable serial port interrupt.
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Bit Bit Number Mnemonic 7 - 6 PPCL PCA interrupt Priority bit Refer to PPCH for priority level. 5 PT2L Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level. 4 PSL Serial port Priority bit Refer to PSH for priority level. 3 PT1L Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. 2 PX1L External interrupt 1 Priority bit Refer to PX1H for priority level. 1 PT0L Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level.
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AT89C5130A/31A-M Bit Bit Number Mnemonic 7 - 6 5 4 3 2 1 0 Description Reserved The value read from this bit is indeterminate. Do not set this bit. PPCH PCA interrupt Priority high bit.
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IEN1 - Interrupt Enable Register (B1h) 7 6 5 4 3 2 1 0 - EUSB - - - ESPI ETWI EKB Bit Bit Number Mnemonic 7 - 6 EUSB 5 - Reserved 4 - Reserved 3 - Reserved 2 ESPI SPI interrupt Enable bit Cleared to disable SPI interrupt. Set to enable SPI interrupt. 1 ETWI TWI interrupt Enable bit Cleared to disable TWI interrupt. Set to enable TWI interrupt. 0 EKB Keyboard interrupt Enable bit Cleared to disable keyboard interrupt. Set to enable keyboard interrupt.
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AT89C5130A/31A-M Reset Value = X0XX X000b Not bit addressable Table 16-6. IPL1 Register IPL1 - Interrupt Priority Register (B2h) 7 6 5 4 3 2 1 0 - PUSBL - - - PSPIL PTWIL PKBDL Bit Bit Number Mnemonic 7 - 6 PUSBL 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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Table 16-7. IPH1 Register IPH1 - Interrupt Priority High Register (B3h) 7 6 5 4 3 2 1 0 - PUSBH - - - PSPIH PTWIH PKBH Bit Bit Number Mnemonic 7 - Description Reserved The value read from this bit is indeterminate. Do not set this bit. USB Interrupt Priority High bit PUSBH PUSBL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest 6 PUSBH 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate.
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AT89C5130A/31A-M 16.3 Interrupt Sources and Vector Addresses Table 16-8.
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17. Keyboard Interface 17.1 Introduction The AT89C5130A/31A-M implements a keyboard interface allowing the connection of a 8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as an alternate function of P1 and allow to exit from idle and power down modes. 17.
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AT89C5130A/31A-M 17.2.2 17.3 Power Reduction Mode P1 inputs allow exit from idle and power down modes as detailed in section “Power-down Mode”. Registers Table 17-1. KBF Register KBF - Keyboard Flag Register (9Eh) 7 6 5 4 3 2 1 0 KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0 Bit Number Bit Mnemonic Description 7 6 5 4 3 2 1 0 KBF7 Keyboard line 7 flag Set by hardware when the Port line 7 detects a programmed level. It generates a Keyboard interrupt request if the KBKBIE.
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Table 17-2. KBE Register KBE - Keyboard Input Enable Register (9Dh) 7 6 5 4 3 2 1 0 KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0 Bit Number Bit Mnemonic Description 7 KBE7 Keyboard line 7 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.7 bit in KBF register to generate an interrupt request. 6 KBE6 Keyboard line 6 Enable bit Cleared to enable standard I/O pin. Set to enable KBF.6 bit in KBF register to generate an interrupt request.
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AT89C5130A/31A-M Table 17-3. KBLS Register KBLS-Keyboard Level Selector Register (9Ch) 7 6 5 4 3 2 1 0 KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0 Bit Number Bit Mnemonic Description 7 KBLS7 Keyboard line 7 Level Selection bit Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7. 6 KBLS6 Keyboard line 6 Level Selection bit Cleared to enable a low level detection on Port line 6.
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18. Programmable LED AT89C5130A/31A-M have up to 4 programmable LED current sources, configured by the register LEDCON. Table 18-1. LEDCON Register LEDCON (S:F1h) LED Control Register 7 6 5 LED3 Bit Number 7:6 5:4 3:2 1:0 4 LED2 Bit Mnemonic 3 2 LED1 1 0 LED0 Description LED3 Port 0 0 1 1 LED3 0 1 0 1 Configuration Standard C51 Port 2 mA current source when P3.7 is low 4 mA current source when P3.7 is low 10 mA current source when P3.
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AT89C5130A/31A-M 19. Serial Peripheral Interface (SPI) The Serial Peripheral Interface module (SPI) allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. 19.
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19.2.3 SPI Serial Clock (SCK) This signal is used to synchronize the data movement both in and out the devices through their MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to exchange one byte on the serial lines. 19.2.4 Slave Select (SS) Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave. It is obvious that only one Master (SS high level) can drive the network.
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AT89C5130A/31A-M 19.3 SPR2 SPR1 SPR0 Clock Rate Baud Rate Divisor (BD) 1 1 1 Don’t Use No BRG Functional Description Figure 19-2 shows a detailed structure of the SPI module. Figure 19-2.
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When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 19-3). Figure 19-3. Full-duplex Master/Slave Interconnection 8-bit Shift Register SPI Clock Generator MISO MISO MOSI MOSI SCK SS Master MCU 8-bit Shift Register SCK VDD SS VSS Slave MCU 19.3.1.
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AT89C5130A/31A-M output data are shifted (Figure 19-4 and Figure 19-5). The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device. Figure 19-4. Data Transmission Format (CPHA = 0) SCK cycle number 1 2 3 4 5 6 7 8 MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB bit6 bit5 bit4 bit3 bit2 bit1 LSB SPEN (internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) MSB SS (to Slave) Capture point Figure 19-5.
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19.3.3 19.3.3.1 Error Conditions The following flags in the SPSTA signal SPI error conditions: Mode Fault (MODF) Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may have a multi-master conflict for system control. In this case, the SPI system is affected in the following ways: • An SPI receiver/error CPU interrupt request is generated, • The SPEN bit in SPCON is cleared.
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AT89C5130A/31A-M Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests. Figure 19-7 gives a logical view of the above statements. Figure 19-7. SPI Interrupt Requests Generation SPIF SPI Transmitter CPU Interrupt Request SPI CPU Interrupt Request MODF SPI Receiver/Error CPU Interrupt Request SSDIS 19.3.
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Bit Number Bit Mnemonic 2 CPHA Description Clock Phase Cleared to have the data sampled when the SCK leaves the idle state (see CPOL). Set to have the data sampled when the SCK returns to idle state (see CPOL). SPR2 SPR1 SPR0 Serial Peripheral Rate 1 000Reserved SPR1 00 1FCLK PERIPH/4 010 FCLK PERIPH/8 011FCLK PERIPH/16 100FCLK PERIPH/32 0 10 1FCLK PERIPH/64 SPR0 110FCLK PERIPH/128 1 11Reserved Reset Value = 0001 0100b Not bit addressable 19.3.5.
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AT89C5130A/31A-M Bit Number Bit Mnemonic Description Mode Fault 4 MODF Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been approved by a clearing sequence. Set by hardware to indicate that the SS pin is at inappropriate logic level. 3 - 2 - 1 - 0 - Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate.
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20. Two Wire Interface (TWI) This section describes the 2-wire interface. The 2-wire bus is a bi-directional 2-wire serial communication standard. It is designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs connected to them. The serial data transfer is limited to 400 Kbit/s in standard mode. Various communication configuration can be designed using this bus.
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AT89C5130A/31A-M Figure 20-2.
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20.1 Description The CPU interfaces to the 2-wire logic via the following four 8-bit special function registers: the Synchronous Serial Control register (SSCON; Table 20-10), the Synchronous Serial Data register (SSDAT; Table 20-11), the Synchronous Serial Control and Status register (SSCS; Table 2012) and the Synchronous Serial Address register (SSADR Table 20-13).
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AT89C5130A/31A-M R : Read bit (high level at SDA) W : Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P : STOP condition In Figure 20-4 to Figure 20-7, circles are used to indicate when the serial interrupt flag is set. The numbers in the circles show the status code held in SSCS. At these points, a service routine must be executed to continue or complete the serial transfer.
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address and the data direction bit (SLA+R). The serial interrupt flag SI must then be cleared before the serial transfer can continue. When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, the serial interrupt flag is set again and a number of status code in SSCS are possible. There are 40h, 48h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1).
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AT89C5130A/31A-M 20.1.4 Slave Transmitter Mode In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (Figure 20-7). Data transfer is initialized as in the slave receiver mode. When SSADR and SSCON have been initialized, the TWI module waits until it is addressed by its own slave address followed by the data direction bit which must be at logic 1 (R) for TWI to operate in the slave transmitter mode.
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Bit Frequency ( kHz) CR2 CR1 CR0 FOSCA= 12 MHz FOSCA = 16 MHz FOSCA divided by 1 0 0 - - Unused 1 0 1 100 133.3 120 1 1 0 200 266.6 60 1 1 1 0.5 <. < 62.5 0.67 <. < 83 Timer 1 in mode 2 can be used as TWI baudrate generator with the following formula: 96.
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AT89C5130A/31A-M Figure 20-4.
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Table 20-5.
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AT89C5130A/31A-M Figure 20-5.
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Table 20-6. Status in Master Receiver Mode Application software response Status Code SSSTA Status of the Twowire Bus and Twowire Hardware To SSCON To/From SSDAT SSSTA SSSTO SSI SSAA Next Action Taken by Two-wire Hardware 08h A START condition has Write SLA+R been transmitted X 0 0 X Write SLA+R X 0 0 X 10h A repeated START condition has been transmitted Write SLA+W X 0 0 X SLA+W will be transmitted. Logic will switch to master transmitter mode.
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AT89C5130A/31A-M Figure 20-6. Format and State in the Slave Receiver Mode Reception of the own slave address and one or more data bytes. All are acknowledged. S SLA W Data A 60h A Data 80h Last data byte received is not acknowledged. A P or S 80h A0h A P or S 88h Arbitration lost as master and addressed as slave A 68h Reception of the general call address and one or more data bytes. General Call Data A 70h Last data byte received is not acknowledged.
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Table 20-7.
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AT89C5130A/31A-M Table 20-7.
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Figure 20-7. Format and State in the Slave Transmitter Mode Reception of the S own slave address and one or more data bytes SLA A R Data A A8h Arbitration lost as master and addressed as slave B8h Data A P or S C0h A B0h Last data byte transmitted. Switched to not addressed slave (AA=0) A All 1’s P or S C8h From master to slave Data From slave to master Table 20-8.
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AT89C5130A/31A-M Table 20-8.
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20.3 Registers Table 20-10. SSCON Register SSCON - Synchronous Serial Control Register (93h) 7 6 5 4 3 2 1 0 CR2 SSIE STA STO SI AA CR1 CR0 Bit Number Bit Mnemonic Description 7 CR2 Control Rate bit 2 See . 6 SSIE Synchronous Serial Interface Enable bit Clear to disable SSLC. Set to enable SSLC. 5 STA Start flag Set to send a START condition on the bus. 4 ST0 Stop flag Set to send a STOP condition on the bus.
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AT89C5130A/31A-M Bit Number Bit Mnemonic 1 SD1 Address bit 1 or Data bit 1. 0 SD0 Address bit 0 (R/W) or Data bit 0. Description Table 20-12.
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21. USB Controller . 21.1 Description The USB device controller provides the hardware that the AT89C5131 needs to interface a USB link to a data flow stored in a double port memory (DPRAM). The USB controller requires a 48 MHz ±0.25% reference clock, which is the output of the AT89C5131 PLL (see Section “PLL”, page 15) divided by a clock prescaler.
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AT89C5130A/31A-M • Address checking. • Clock generation (via DPLL). Figure 21-2. SIE Block Diagram End of Packet Detection SYNC Detection Start of Packet Detection PID Decoder NRZI ‘NRZ Bit Un-stuffing Packet Bit Counter D+ D- Clock Recovery Clk48 (48 MHz) Address Decoder DataOut 8 Serial to Parallel SysClk (12 MHz) CRC5 and CRC16 Generation/Check USB Pattern Generator Parallel to Serial Converter Bit Stuffing NRZI Converter 8 DataIn [7:0] CRC16 Generator 21.1.
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Figure 21-3. UFI Block Diagram FIU DPLL Asynchronous Information CSREG 0 to 7 Transfer Transfer Control Endpoint 6 Registers FSM Endpoint 5 Bank Endpoint 4 Endpoint 3 Endpoint 2 Endpoint 1 Endpoint 0 DPR Control USB Side SIE DPR Control mP side C51 Microcontroller Interface Up to 48 MHz UC_sysclk User DPRAM Figure 21-4.
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AT89C5130A/31A-M • Set configuration The CONFG bit in the USBCON register has to be set after a SET_CONFIGURATION request with a non-zero value. Otherwise, this bit has to be cleared. 21.2.2 Endpoint Configuration • Selection of an Endpoint The endpoint register access is performed using the UEPNUM register. The registers – UEPSTAX – UEPCONX – UEPDATX – UBYCTLX – UBYCTHX These registers correspond to the endpoint whose number is stored in the UEPNUM register.
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The Endpoint 0 is the Default Control Endpoint and will always be configured in Control type. • Endpoint direction configuration For Bulk, Interrupt and Isochronous endpoints, the direction is defined with the EPDIR bit of the UEPCONX register with the following values: – IN:EPDIR = 1b – OUT:EPDIR = 0b For Control endpoints, the EPDIR bit has no effect.
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AT89C5130A/31A-M Figure 21-6. Endpoint FIFO Configuration Endpoint 0 Endpoint 6 UEPSTA0 UEPCON0 UBYCTH0 UEPSTA6 0 SFR registers UBYCTL0 UEPCON6 UBYCTH6 UEPDAT0 UEPDAT6 1 2 3 4 5 6 X UEPSTAX UEPCONX UBYCTHX UEPDATX UBYCTLX UBYCTL6 UEPNUM 21.3.2 Read Data FIFO The read access for each OUT endpoint is performed using the UEPDATX register.
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21.4.1 Bulk/Interrupt OUT Transactions in Standard Mode Figure 21-7. Bulk/Interrupt OUT transactions in Standard Mode HOST OUT C51 UFI DATA0 (n bytes) ACK RXOUTB0 Endpoint FIFO read byte 1 OUT DATA1 Endpoint FIFO read byte 2 NAK OUT Endpoint FIFO read byte n DATA1 Clear RXOUTB0 NAK OUT DATA1 ACK RXOUTB0 Endpoint FIFO read byte 1 An endpoint will be first enabled and configured before being able to receive Bulk or Interrupt packets.
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AT89C5130A/31A-M 21.4.2 Bulk/Interrupt OUT Transactions in Ping-pong Mode Figure 21-8.
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A NAK handshake is sent by the USB controller only if the banks 0 and 1 has not been released by the firmware. If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct. 21.4.3 Bulk/Interrupt IN Transactions in Standard Mode Figure 21-9.
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AT89C5130A/31A-M 21.4.4 Bulk/Interrupt IN Transactions in Ping-pong Mode Figure 21-10.
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The firmware will never write more bytes than supported by the endpoint FIFO. 21.5 21.5.1 Control Transactions Setup Stage The DIR bit in the UEPSTAX register will be at 0. Receiving Setup packets is the same as receiving Bulk Out packets, except that the RXSETUP bit in the UEPSTAX register is set by the USB controller instead of the RXOUTB0 bit to indicate that an Out packet with a Setup PID has been received on the Control endpoint.
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AT89C5130A/31A-M 21.6 21.6.1 Isochronous Transactions Isochronous OUT Transactions in Standard Mode An endpoint will be first enabled and configured before being able to receive Isochronous packets. When a OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled. The firmware has to select the corresponding endpoint, store the number of data bytes by reading the UBYCTLX and UBYCTHX registers.
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The firmware has to clear one of these two bits after having read all the data FIFO to allow a new packet to be stored in the corresponding bank. If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct. 21.6.3 Isochronous IN Transactions in Standard Mode An endpoint will be first enabled and configured before being able to send Isochronous packets.
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AT89C5130A/31A-M 21.7.2 STALL Handshake This function is only available for Control, Bulk, and Interrupt endpoints. The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL handshake at the next request of the Host on the endpoint selected with the UEPNUM register. The RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first reset to 0. The bit STLCRC is set at 1 by the USB controller when a STALL has been sent. This triggers an interrupt if enabled.
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The stop of the 48 MHz clock from the PLL should be done in the following order: 1. Clear suspend interrupt bit in USBINT (required to allow the USB pads to enter power down mode). 2. Enable USB resume interrupt. 3. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUSPCLK bit in the USBCON register. 4. Disable the PLL by clearing the PLLEN bit in the PLLCON register. 5. Make the CPU core enter power down mode by setting PDOWN bit in PCON. 21.8.
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AT89C5130A/31A-M When the USB controller receives the SET_FEATURE request: DEVICE_REMOTE_WAKEUP, the firmware will set to 1 the RMWUPE bit in the USBCON register to enable this functionality. RMWUPE value will be 0 in the other cases. If the device is in SUSPEND mode, the USB controller can send an upstream resume by clearing first the SPINT bit in the USBINT register and by setting then to 1 the SDRMWUP bit in the USBCON register. The USB controller sets to 1 the UPRSM bit in the USBCON register.
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Figure 21-13. Example of VREF Connection VREF 1.5 kW 1 2 DD+ 3 4 AT89C5131 VCC DD+ GND USB-B Connector Figure 21-14. Disconnect Timing D+ VIHZ(min) VIL VSS D> = 2,5 ms Disconnect Detected Device Disconnected 21.10 USB Interrupt System 21.10.1 Interrupt System Priorities Figure 21-15. USB Interrupt Control System D+ D- 00 01 10 11 USB Controller EUSB EA IE1.6 IE0.7 IPH/L Priority Enable Interrupt Enable Table 21-2.
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AT89C5130A/31A-M 21.10.2 USB Interrupt Control System As shown in Figure 21-16, many events can produce a USB interrupt: • TXCMPL: Transmitted In Data (see Table 21-9 on page 144). This bit is set by hardware when the Host accept a In packet. • RXOUTB0: Received Out Data Bank 0 (see Table 21-9 on page 144). This bit is set by hardware when an Out packet is accepted by the endpoint and stored in bank 0. • RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (see Table 21-9 on page 144).
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Figure 21-16. USB Interrupt Control Block Diagram Endpoint X (X = 0..6) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 EPXINT UEPINT.X RXOUTB1 UEPSTAX.6 EPXIE UEPIEN.X RXSETUP UEPSTAX.2 STLCRC UEPSTAX.3 WUPCPU USBINT.5 EWUPCPU USBIEN.5 EUSB IE1.6 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 SPINT USBINT.0 ESPINT USBIEN.
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AT89C5130A/31A-M 21.11 USB Registers Table 21-3. USBCON Register USBCON (S:BCh) USB Global Control Register 7 6 5 4 3 2 1 0 USBE SUSPCLK SDRMWUP DETACH UPRSM RMWUPE CONFG FADDEN Bit Number Bit Mnemonic 7 USBE 6 SUSPCLK 5 4 3 2 Description USB Enable Set this bit to enable the USB controller. Clear this bit to disable and reset the USB controller, to disable the USB transceiver an to disable the USB controller clock inputs.
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Table 21-4. USBINT Register USBINT (S:BDh) USB Global Interrupt Register 7 6 5 4 3 2 1 0 - - WUPCPU EORINT SOFINT - - SPINT Bit Number Bit Mnemonic Description 7-6 - 5 WUPCPU Reserved The value read from these bits is always 0. Do not set these bits. Wake Up CPU Interrupt This bit is set by hardware when the USB controller is in SUSPEND state and is reactivated by a non-idle signal FROM USB line (not by an upstream resume).
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AT89C5130A/31A-M Table 21-5. USBIEN Register USBIEN (S:BEh) USB Global Interrupt Enable Register 7 6 5 4 3 2 1 0 - - EWUPCPU EEORINT ESOFINT - - ESPINT Bit Number Bit Mnemonic 7-6 - 5 EWUPCPU Description Reserved The value read from these bits is always 0. Do not set these bits. Enable Wake Up CPU Interrupt Set this bit to enable Wake Up CPU Interrupt. (See “USBIEN Register USBIEN (S:BEh) USB Global Interrupt Enable Register” on page 141.
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Table 21-6. USBADDR Register USBADDR (S:C6h) USB Address Register 7 6 5 4 3 2 1 0 FEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 Bit Number Bit Mnemonic Description 7 FEN 6-0 UADD[6:0] Function Enable Set this bit to enable the address filtering function. Cleared this bit to disable the function. USB Address This field contains the default address (0) after power-up or USB bus reset. It will be written with the value set by a SET_ADDRESS request received by the device firmware.
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AT89C5130A/31A-M Table 21-8. UEPCONX Register UEPCONX (S:D4h) USB Endpoint X Control Register 7 6 5 4 3 2 1 0 EPEN - - - DTGL EPDIR EPTYPE1 EPTYPE0 Bit Number Endpoint Enable Set this bit to enable the endpoint according to the device configuration. Endpoint 0 will always be enabled after a hardware or USB bus reset and participate in the device configuration. Clear this bit to disable the endpoint according to the device configuration.
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Table 21-9. Bit Number Bit Mnemonic UEPSTAX (S:CEh) USB Endpoint X Status Register 7 6 5 4 3 2 1 0 DIR RXOUTB1 STALLRQ TXRDY STL/CRC RXSETUP RXOUTB0 TXCMP Description DIR Control Endpoint Direction This bit is used only if the endpoint is configured in the control type (seeSection “UEPCONX Register UEPCONX (S:D4h) USB Endpoint X Control Register”). This bit determines the Control data and status direction.
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AT89C5130A/31A-M Table 21-10. UEPDATX Register UEPDATX (S:CFh) USB FIFO Data Endpoint X (X = EPNUM set in UEPNUM Register UEPNUM 7 6 5 4 3 2 1 0 FDAT7 FDAT6 FDAT5 FDAT4 FDAT3 FDAT2 FDAT1 FDAT0 Bit Number Bit Mnemonic Description 7-0 FDAT[7:0] Endpoint X FIFO data Data byte to be written to FIFO or data byte to be read from the FIFO, for the Endpoint X (see EPNUM). (S:C7h) USB Endpoint Number) Reset Value = XXh Table 21-11.
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Table 21-12. UBYCTHX Register UBYCTHX (S:E3h) USB Byte Count High Register X (X = EPNUM set in UEPNUM Register UEP- 7 6 5 4 3 2 1 0 - - - - - - BYCT9 BYCT8 Bit Number 7-2 2-0 Bit Mnemonic Description - BYCT[10:8] Reserved The value read from these bits is always 0. Do not set these bits. Byte Count MSB Most Significant Byte of the byte count of a received data packet.
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AT89C5130A/31A-M Table 21-13. UEPRST Register UEPRST (S:D5h) USB Endpoint FIFO Reset Register 7 6 5 4 3 2 1 0 - EP6RST EP5RST EP4RST EP3RST EP2RST EP1RST EP0RST Bit Number Bit Mnemonic Description 7 - 6 5 4 3 2 1 0 Reserved The value read from this bit is always 0. Do not set this bit. EP6RST Endpoint 6 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset or when an USB bus reset has been received.
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Table 21-14. UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register 7 6 5 4 3 2 1 0 - EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is always 0. Do not set this bit. Endpoint 6 Interrupt 6 EP6INT This bit is set by hardware when an endpoint interrupt source has been detected on the endpoint 6.
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AT89C5130A/31A-M Table 21-15. UEPIEN Register UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register 7 6 5 4 3 2 1 0 - EP6INTE EP5INTE EP4INTE EP3INTE EP2INTE EP1INTE EP0INTE Bit Number Bit Mnemonic Description 7 - 6 EP6INTE Endpoint 6 Interrupt Enable Set this bit to enable the interrupts for this endpoint. Clear this bit to disable the interrupts for this endpoint. 5 EP5INTE Endpoint 5 Interrupt Enable Set this bit to enable the interrupts for this endpoint.
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Table 21-16. UFNUMH Register UFNUMH (S:BBh, read-only) USB Frame Number High Register 7 6 5 4 3 2 1 0 - - CRCOK CRCERR - FNUM10 FNUM9 FNUM8 Bit Number 5 Bit Mnemonic Description CRCOK 4 CRCERR 3 - 2-0 Frame Number CRC OK This bit is set by hardware when a new Frame Number in Start of Frame Packet is received without CRC error. This bit is updated after every Start of Frame packet receipt. Important note: the Start of Frame interrupt is generated just after the PID receipt.
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AT89C5130A/31A-M 22. Reset 22.1 Introduction The reset sources are: Power Management, Hardware Watchdog, PCA Watchdog and Reset input. Figure 22-1. Reset schematic Power Monitor Hardware Watchdog Internal Reset PCA Watchdog RST 22.2 Reset Input The Reset input can be used to force a reset pulse longer than the internal reset controlled by the Power Monitor. RST input has a pull-up resistor allowing power-on reset by simply connecting an external capacitor to V S S as shown in Figure 22-2.
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Figure 22-3.
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AT89C5130A/31A-M 23. Power Monitor The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an internal reset to them. By generating the Reset the Power Monitor insures a correct start up when AT89C5131 is powered up. 23.
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Figure 23-2. Power Fail Detect Vcc t Reset Vcc When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input. The internal reset will remain asserted until the Xtal1 levels are above and below VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is de-asserted.
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AT89C5130A/31A-M 24. Power Management 24.1 Idle Mode An instruction that sets PCON.0 indicates that it is the last instruction to be executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain their data during Idle.
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Figure 24-1. Power-down Exit Waveform INT0 INT1 XTAL Active Phase Power-down Phase Oscillator restart Phase Active Phase Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs. Exit from power-down by either reset or external interrupt does not affect the internal RAM content.
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AT89C5130A/31A-M 24.3 Registers Table 24-2. PCON Register PCON (S:87h) Power Control Register 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7 SMOD1 Serial Port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial Port Mode bit 0 Set to select FE bit in SCON register. Clear to select SM0 bit in SCON register 5 - Reserved The value read from this bit is always 0. Do not set this bit.
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25. Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H.
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AT89C5130A/31A-M Table 25-2. WDTPRG Register WDTPRG - Watchdog Timer Out Register (0A7h) 7 6 5 4 3 2 1 0 - - - - - S2 S1 S0 Bit Bit Number Mnemonic 7 - 6 - 5 - 4 - 3 - 2 S2 WDT Time-out select bit 2 1 S1 WDT Time-out select bit 1 0 S0 WDT Time-out select bit 0 Description Reserved The value read from this bit is undetermined. Do not try to set this bit. S2 S1 S0 Selected Time-out 0 0 0 16384x2^(214 - 1) machine cycles, 16.
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26. Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches.
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AT89C5130A/31A-M 27. Electrical Characteristics 27.1 Absolute Maximum Ratings Note: Ambient Temperature Under Bias: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. I = industrial .
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Notes: 1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 27-4.), VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure 27-1.). 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC 0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 27-2). 3.
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AT89C5130A/31A-M Figure 27-3. ICC Test Condition, Power-down Mode VCC ICC VCC VCC P0 VCC RST (NC) EA XTAL2 XTAL1 VSS All other pins are disconnected. Figure 27-4. Clock Signal Waveform for ICC Tests in Active and Idle Modes VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 27.2.1 LED’s Table 27-1. Symbol IOL 0.7VCC 0.2VCC-0.1 LED Outputs DC Parameters Parameter Output Low Current, P3.6 and P3.7 LED modes Note: 1. (TA = -20°C to +50°C, VCC - VOL = 2 V ± 20%) 27.
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Symbol Parameter Min Max Unit USB Reference Voltage 3.0 3.6 V VIH Input High Voltage for D+ and D- (Driven) 2.0 4.0 V VIHZ Input High Voltage for D+ and D- (Floating) 2.7 3.6 V VIL Input Low Voltage for D+ and D- 0.8 V VOH Output High Voltage for D+ and D- 2.8 3.6 V VOL Output Low Voltage for D+ and D- 0.0 0.3 V VREF 27.4 27.4.1 Typ AC Parameters Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time).
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AT89C5130A/31A-M 27.4.2 External Program Memory Characteristics Table 27-2.
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Table 27-4. 27.4.3 AC Parameters for a Variable Clock Symbol Type Standard Clock X2 Clock X Parameter Units TLHLL Min 2T-x T-x 10 ns TAVLL Min T-x 0.5 T - x 15 ns TLLAX Min T-x 0.5 T - x 15 ns TLLIV Max 4T-x 2T-x 30 ns TLLPL Min T-x 0.5 T - x 10 ns TPLPH Min 3T-x 1.5 T - x 20 ns TPLIV Max 3T-x 1.5 T - x 40 ns TPXIX Min x x 0 ns TPXIZ Max T-x 0.5 T - x 7 ns TAVIV Max 5T-x 2.
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AT89C5130A/31A-M 27.4.4 External Data Memory Characteristics Table 27-5.
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Table 27-7. 27.4.5 AC Parameters for a Variable Clock Symbol Type Standard Clock X2 Clock X Parameter Units TRLRH Min 6T-x 3T-x 20 ns TWLWH Min 6T-x 3T-x 20 ns TRLDV Max 5T-x 2.5 T - x 25 ns TRHDX Min x x 0 ns TRHDZ Max 2T-x T-x 20 ns TLLDV Max 8T-x 4T -x 40 ns TAVDV Max 9T-x 4.5 T - x 60 ns TLLWL Min 3T-x 1.5 T - x 25 ns TLLWL Max 3T+x 1.5 T + x 25 ns TAVWL Min 4T-x 2T-x 25 ns TQVWX Min T-x 0.5 T - x 15 ns TQVWH Min 7T-x 3.
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AT89C5130A/31A-M 27.4.6 External Data Memory Read Cycle TWHLH TLLDV ALE PSEN TLLWL TRLRH RD TRHDZ TAVDV TLLAX PORT 0 TRHDX A0-A7 DATA IN TAVWL PORT 2 27.4.7 ADDRESS OR SFR-P2 TRLAZ ADDRESS A8-A15 OR SFR P2 Serial Port Timing - Shift Register Mode Table 27-8. Symbol Description (F = 40 MHz) Symbol Table 27-9.
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27.4.8 Shift Register Timing Waveform 0 INSTRUCTION 1 2 3 4 5 6 7 8 ALE TXLXL CLOCK TXHQX TQVXH 0 OUTPUT DATA 1 2 INPUT DATA 4 5 6 TXHDX TXHDV WRITE to SBUF 3 VALID VALID SET TI VALID VALID VALID VALID VALID External Clock Drive Characteristics (XTAL1) Table 27-11. AC Parameters Symbol Parameter Min Max Units TCLCL Oscillator Period 21 ns TCHCX High Time 5 ns TCLCX Low Time 5 ns TCLCH Rise Time 5 ns TCHCL Fall Time 5 ns 60 % TCHCX/TCLCX 27.4.
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AT89C5130A/31A-M 27.4.13 Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
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27.4.14 Flash EEPROM Memory and Data EEPROM Memory Table 27-12. Timing Symbol Definitions Signals Conditions S (Hardware Condition) PSEN, EA L Low R RST V Valid B FBUSY Flag X No Longer Valid Table 27-13. Memory AC Timing Vcc = 3.
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AT89C5130A/31A-M 27.5 USB AC Parameters Rise Time Fall Time 90% VHmin 90% VCRS 10% 10% Differential Data Lines VLmax tF tR Table 27-14. USB AC Parameters Symbol Parameter Min tR Rise Time tF Fall Time Max Unit 4 20 ns 4 20 ns 11.9700 12.0300 Mb/s Crossover Voltage 1.3 2.0 V tDJ1 Source Jitter Total to Next Transaction -3.5 3.5 ns tDJ2 Source Jitter Total for Paired Transactions -4 4 ns tJR1 Receiver Jitter to Next Transaction -18.5 18.
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VDD = 2.7 to 5.5 V, TA = -40 to +85°C Symbol Parameter Min Max Unit Slave Mode TCHCH Clock Period 2 TPER TCHCX Clock High Time 0.8 TPER TCLCX Clock Low Time 0.
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AT89C5130A/31A-M 27.6.0.3 Waveforms Figure 27-7. SPI Slave Waveforms (CPHA= 0) SS (input) TSLCH TSLCL TCHCH SCK (CPOL= 0) (input) TCHCX TSHSL TCLCX TCHCL SCK (CPOL= 1) (input) TCLOX TCHOX TCLOV TCHOV TSLOV MISO (output) TCLCH TCLSH TCHSH SLAVE MSB OUT BIT 6 TSHOX SLAVE LSB OUT (1) TIVCH TCHIX TIVCL TCLIX MOSI (input) Note: MSB IN BIT 6 LSB IN 1. Not Defined but generally the MSB of the character which has just been received. Figure 27-8.
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Figure 27-9. SPI Master Waveforms (SSCPHA= 0) SS (output) TCHCH SCK (CPOL= 0) (output) TCHCX TCLCH TCLCX TCHCL SCK (CPOL= 1) (output) TIVCH TCHIX TIVCL TCLIX MOSI (input) MSB IN BIT 6 LSB IN TCLOX TCLOV TCHOV MISO (output) Note: Port Data MSB OUT TCHOX BIT 6 LSB OUT Port Data 1. SS handled by software using general purpose port pin. Figure 27-10.
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AT89C5130A/31A-M 28. Ordering Information Table 28-1. Possible Order Entries Part Number Memory Size (Kbytes) Supply Voltage Temperature Range Package Packing AT89C5130A-RDTUM 16 2.7 to 5.5V Industrial & Green VQFP64 Tray & Dry Pack AT89C5130A-PUTUM 16 2.7 to 5.5V Industrial & Green QFN32 Tray & Dry Pack AT89C5130A-S3SUM 16 2.7 to 5.5V Industrial & Green PLCC52 Stick AT89C5131A-RDTUM 32 2.7 to 5.5V Industrial & Green VQFP64 Tray & Dry Pack AT89C5131A-PUTUM 32 2.7 to 5.
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29. Packaging Information 29.
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AT89C5130A/31A-M STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP 1/ CONTROLLING DIMENSIONS : INCHES 2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M 1982. 3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT EXCEED 0.25 mm (0.010 INCH). THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE BODY SIZE BY AS MUCH AS 0.15 mm. 4/ DATUM PLANE "H" LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE.
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29.2 52-lead PLCC STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER SIDE.
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AT89C5130A/31A-M 29.
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AT89C5130A/31A-M 4337K–USB–04/08
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AT89C5130A/31A-M 30. Datasheet Revision History 30.1 Changes from 4337F to 4337G 1. Added warning regarding hardware conditions on startup, see page 48. 30.2 Changes from 4337G to 4337H 1. Hardware Conditions section Page 46 changed to recommend the use of 1K pull-up between PSEN and GND in ISP mode. 2. Updated 52-lead PLCC package drawing. 30.3 Changes from 4337H to 4337I 1. Correction to Kbit/s value See “Two Wire Interface (TWI)” on page 102. 2. Package Drawings updated. 30.
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Table of Contents 1 Description ............................................................................................... 2 2 Block Diagram .......................................................................................... 3 3 Pinout Description ................................................................................... 4 4 5 3.1 Pinout ................................................................................................................4 3.2 Signals .............
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AT89C5130A/31A-M 10.3 Programming ...................................................................................................43 10.4 Read Data .......................................................................................................43 10.5 Registers .........................................................................................................44 11 In-System Programming (ISP) .............................................................. 45 11.
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19 Serial Peripheral Interface (SPI) ............................................................ 93 19.1 Features ..........................................................................................................93 19.2 Signal Description ............................................................................................93 19.3 Functional Description .....................................................................................95 20 Two Wire Interface (TWI) ...................
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AT89C5130A/31A-M 27 Electrical Characteristics .................................................................... 161 27.1 Absolute Maximum Ratings ..........................................................................161 27.2 DC Parameters ..............................................................................................161 27.3 USB DC Parameters .....................................................................................163 27.4 AC Parameters .............................
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Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg.