Datasheet

64
32099IS–01/2012
AT32UC3L016/32/64
7.9.3 USART in SPI Mode Timing
7.9.3.1 Master mode
Figure 7-8. USART in SPI Master Mode With (CPOL= CPHA= 0) or (CPOL= CPHA= 1)
Figure 7-9. USART in SPI Master Mode With (CPOL= 0 and CPHA= 1) or (CPOL= 1 and
CPHA= 0)
Notes: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
2. Where:
USPI0 USPI1
MISO
SPCK
MOSI
USPI2
USPI3 USPI4
MISO
SPCK
MOSI
USPI5
Table 7-38. USART in SPI Mode Timing, Master Mode
(1)
Symbol Parameter Conditions Min Max Units
USPI0 MISO setup time before SPCK rises
V
VDDIO
from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
30.0+ t
SAMPLE
(2)
ns
USPI1 MISO hold time after SPCK rises 0
USPI2 SPCK rising to MOSI delay 8.5
USPI3 MISO setup time before SPCK falls 25.5 + t
SAMPLE
(2)
USPI4 MISO hold time after SPCK falls 0
USPI5 SPCK falling to MOSI delay 13.6
t
SAMPLE
t
SPCK
t
SPCK
2 t
CLKUSART
×
------------------------------------
1
2
---
⎝⎠
⎛⎞
t
CLKUSART
×–=