Datasheet
69
32099IS–01/2012
AT32UC3L016/32/64
Figure 7-16. SPI Slave Mode With (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)
Figure 7-17. SPI Slave Mode NPCS Timing
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Maximum SPI Frequency, Slave Input Mode
SPI10 SPI11
MISO
SPCK
MOSI
SPI9
SPI14
SPI12
SPI15
SPI13
NPCS
SPCK, CPOL=0
SPCK, CPOL=1
Table 7-41. SPI Timing, Slave Mode
(1)
Symbol Parameter Conditions Min Max Units
SPI6 SPCK falling to MISO delay
V
VDDIO
from
3.0V to 3.6V,
maximum
external
capacitor =
40pF
30.8
ns
SPI7 MOSI setup time before SPCK rises 0
SPI8 MOSI hold time after SPCK rises 4.1
SPI9 SPCK rising to MISO delay 29.9
SPI10 MOSI setup time before SPCK falls 0
SPI11 MOSI hold time after SPCK falls 3.5
SPI12 NPCS setup time before SPCK rises 1.9
SPI13 NPCS hold time after SPCK falls 0.2
SPI14 NPCS setup time before SPCK falls 2.2
SPI15 NPCS hold time after SPCK rises 0