Datasheet

70
32099IS–01/2012
AT32UC3L016/32/64
The maximum SPI slave input frequency is given by the following formula:
Where is the MOSI setup and hold time, SPI7 + SPI8 or SPI10 + SPI11 depending on
CPOL and NCPHA. is the maximum frequency of the CLK_SPI. Refer to the SPI chap-
ter for a description of this clock.
Maximum SPI Frequency, Slave Output Mode
The maximum SPI slave output frequency is given by the following formula:
Where is the MISO delay, SPI6 or SPI9 depending on CPOL and NCPHA. is the
SPI master setup time. Please refer to the SPI master datasheet for . is the max-
imum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the
maximum frequency of the pins.
7.9.5 TWIM/TWIS Timing
Figure 7-42 shows the TWI-bus timing requirements and the compliance of the device with
them. Some of these requirements (t
r
and t
f
) are met by the device without requiring user inter-
vention. Compliance with the other requirements (t
HD-STA
, t
SU-STA
, t
SU-STO
, t
HD-DAT
, t
SU-DAT-TWI
, t
LOW-
TWI
, t
HIGH
, and f
TWCK
) requires user intervention through appropriate programming of the relevant
TWIM and TWIS user interface registers. Please refer to the TWIM and TWIS sections for more
information.
f
SPCKMAX
MIN f
CLKSPI
1
SPIn
------------(,)=
SPIn
f
CLKSPI
f
SPCKMAX
MIN f
PINMAX
1
SPIn t
SETUP
+
------------------------------------(, )=
SPIn
t
SETUP
t
SETUP
f
PINMAX
Table 7-42. TWI-Bus Timing Requirements
Symbol Parameter Mode
Minimum Maximum
UnitRequirement Device Requirement Device
t
r
TWCK and TWD rise time
Standard
(1)
- 1000
ns
Fast
(1)
20 + 0.1C
b
300
t
f
TWCK and TWD fall time
Standard - 300
ns
Fast 20 + 0.1C
b
300
t
HD-STA
(Repeated) START hold time
Standard 4
t
clkpb
- μs
Fast 0.6
t
SU-STA
(Repeated) START set-up time
Standard 4.7
t
clkpb
- μs
Fast 0.6
t
SU-STO
STOP set-up time
Standard 4.0
4t
clkpb
- μs
Fast 0.6
t
HD-DAT
Data hold time
Standard
0.3
(2)
2t
clkpb
3.45
()
15t
prescaled
+ t
clkpb
μs
Fast 0.9
()