Datasheet

43
32099IS–01/2012
AT32UC3L016/32/64
– Corresponds to the 3.3V supply mode with 1.8V regulated I/O lines, please refer to
the Supply and Startup Considerations section for more details
• Equivalent to the 3.3V single supply mode
• Consumption in 1.8V single supply mode can be estimated by subtracting the regula-
tor static current
• Operating conditions external core supply (Figure 7-2) - used only when noted
–V
VDDIN
= V
VDDCORE
= 1.8V
– Corresponds to the 1.8V single supply mode, please refer to the Supply and Startup
Considerations section for more details
•T
A = 25°C
• Oscillators
– OSC0 (crystal oscillator) stopped
– OSC32K (32KHz crystal oscillator) running with external 32KHz crystal
– DFLL running at 50MHz with OSC32K as reference
• Clocks
– DFLL used as main clock source
– CPU, HSB, and PBB clocks undivided
– PBA clock divided by 4
– The following peripheral clocks running
• PM, SCIF, AST, FLASHCDW, PBA bridge
– All other peripheral clocks stopped
• I/Os are inactive with internal pull-up
• Flash enabled in high speed mode
• POR33 disabled