Datasheet

32
32099IS–01/2012
AT32UC3L016/32/64
5. Memories
5.1 Embedded Memories
• Internal high-speed flash
– 64Kbytes (AT32UC3L064)
– 32Kbytes (AT32UC3L032)
– 16Kbytes (AT32UC3L016)
• 0 wait state access at up to 25mhz in worst case conditions
• 1 wait state access at up to 50mhz in worst case conditions
• Pipelined flash architecture, allowing burst reads from sequential Flash locations, hiding
penalty of 1 wait state access
• Pipelined flash architecture typically reduces the cycle penalty of 1 wait state operation
to only 8% compared to 0 wait state operation
• 100 000 write cycles, 15-year data retention capability
• Sector lock capabilities, bootloader protection, security bit
• 32 fuses, erased during chip erase
• User page for data to be preserved during chip erase
• Internal high-speed SRAM, single-cycle access at full speed
– 16Kbytes (AT32UC3L064, AT32UC3L032)
– 8Kbytes (AT32UC3L016)
5.2 Physical Memory Map
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented
translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space
is mapped as follows:
Table 5-1. AT32UC3L016/32/64 Physical Memory Map
Device Start Address
Size
AT32UC3L064 AT32UC3L032 AT32UC3L016
Embedded SRAM 0x00000000 16Kbytes 16Kbytes 8Kbytes
Embedded Flash 0x80000000 64Kbytes 32Kbytes 16Kbytes
SAU Channels 0x90000000 256 bytes 256 bytes 256 bytes
HSB-PB Bridge B 0xFFFE0000 64Kbytes 64Kbytes 64Kbytes
HSB-PB Bridge A 0xFFFF0000 64Kbytes 64Kbytes 64Kbytes
Table 5-2. Flash Memory Parameters
Part Number Flash Size (FLASH_PW)
Number of pages
(FLASH_P)
Page size
(FLASH_W)
AT32UC3L064 64Kbytes 256 256 bytes
AT32UC3L032 32Kbytes 128 256 bytes
AT32UC3L016 16Kbytes 64 256 bytes