Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 48 (7x7) 32-Bit 50 MHz I/O number 36

Features

• High-performance, Low-power 32-bit Atmel

AVR

Microcontroller

– Compact Single-cycle RISC Instruction Set Including DSP Instructions

– Read-modify-write Instructions and Atomic Bit Manipulation

– Performance

• Up to 64DMIPS Running at 50MHz from Flash (1 Flash Wait State)

• Up to 36DMIPS Running at 25MHz from Flash (0 Flash Wait State)

– Memory Protection Unit (MPU)

• Secure Access Unit (SAU) providing User-defined Peripheral Protection

• picoPower

Technology for Ultra-low Power Consumption

• Multi-hierarchy Bus System

– High-performance Data Transfers on Separate Buses for Increased Performance

– 12 Peripheral DMA Channels Improve Speed for Peripheral Communication

• Internal High-speed Flash

– 64Kbytes, 32Kbytes, and 16Kbytes Versions

– Single-cycle Access up to 25MHz

– FlashVault Technology Allows Pre-programmed Secure Library Support for End

User Applications

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 100,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User-defined Configuration Area

• Internal High-speed SRAM, Single-cycle Access at Full Speed

– 16Kbytes (64Kbytes and 32Kbytes Flash), or 8Kbytes (16Kbytes Flash)

• Interrupt Controller (INTC)

– Autovectored Low-latency Interrupt Service with Programmable Priority

• External Interrupt Controller (EIC)

• Peripheral Event System for Direct Peripheral to Peripheral Communication

• System Functions

– Power and Clock Manager

– SleepWalking Power Saving Control

– Internal System RC Oscillator (RCSYS)

– 32KHz Oscillator

– Multipurpose Oscillator and Digital Frequency Locked Loop (DFLL)

• Windowed Watchdog Timer (WDT)

• Asynchronous Timer (AST) with Real-time Clock Capability

– Counter or Calendar Mode Supported

• Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency

• Six 16-bit Timer/Counter (TC) Channels

– External Clock Inputs, PWM, Capture, and Various Counting Capabilities

• 36 PWM Channels (PWMA)

– 8-bit PWM with a Source Clock up to 150MHz

• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– Independent Baudrate Generator, Support for SPI

– Support for Hardware Handshaking

• One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals

– Up to 15 SPI Slaves can be Addressed

• Two Master and Two Slave Two-wire Interface (TWI), 400kbit/s I

C-compatible

• One 8-channel Analog-to-digital Converter (ADC) with up to 12 Bits Resolution

– Internal Temperature Sensor

32099IS–01/2012

32-bit Atmel

AVR

Microcontroller

AT32UC3L064

AT32UC3L032

AT32UC3L016

Summary

Summary of content (113 pages)

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Features • High-performance, Low-power 32-bit Atmel® AVR® Microcontroller • • • • • • • • • • • • • • • • • – Compact Single-cycle RISC Instruction Set Including DSP Instructions – Read-modify-write Instructions and Atomic Bit Manipulation – Performance • Up to 64DMIPS Running at 50MHz from Flash (1 Flash Wait State) • Up to 36DMIPS Running at 25MHz from Flash (0 Flash Wait State) – Memory Protection Unit (MPU) • Secure Access Unit (SAU) providing User-defined Peripheral Protection picoPower® Technolo
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AT32UC3L016/32/64 • Eight Analog Comparators (AC) with Optional Window Detection • Capacitive Touch (CAT) Module • • • • • – Hardware-assisted Atmel® AVR® QTouch® and Atmel® AVR® QMatrix Touch Acquisition – Supports QTouch and QMatrix Capture from Capacitive Touch Sensors QTouch Library Support – Capacitive Touch Buttons, Sliders, and Wheels – QTouch and QMatrix Acquisition On-chip Non-intrusive Debug System – Nexus Class 2+, Runtime Control, Non-intrusive Data and Program Trace – aWire Single-pin Progr
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AT32UC3L016/32/64 1. Description The Atmel® AVR® AT32UC3L016/32/64 is a complete system-on-chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and high performance.
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AT32UC3L016/32/64 The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing it to a known reference clock. The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation.
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AT32UC3L016/32/64 2.
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AT32UC3L016/32/64 2.2 Configuration Summary Table 2-1.
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AT32UC3L016/32/64 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Section 3.2. TQFP48/QFN48 Pinout 36 35 34 33 32 31 30 29 28 27 26 25 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 Figure 3-1.
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AT32UC3L016/32/64 TLLGA48 Pinout 37 36 35 34 33 32 31 30 29 28 27 26 25 PA15 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 Figure 3-2.
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AT32UC3L016/32/64 3.2 Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed signals Each GPIO line can be assigned to one of the peripheral functions.The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1.
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AT32UC3L016/32/64 Table 3-1.
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AT32UC3L016/32/64 Refer to the ”TWI Pin Characteristics(1)” on page 49 for a description of the electrical properties of the TWI, 5V Tolerant, and SMBUS pins. 3.2.2 Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed function has priority in case multiple functions are enabled on the same pin. Table 3-2. 3.2.
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AT32UC3L016/32/64 Table 3-4. 3.2.5 Pin AXS=1 AXS=0 MDO[1] PA15 PB02 MDO[0] PA14 PB09 EVTO_N PA04 PA04 MCKO PA06 PB01 MSEO[1] PA07 PB11 MSEO[0] PA11 PB12 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more information about this. Table 3-5. 3.2.
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AT32UC3L016/32/64 3.3 Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-7.
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AT32UC3L016/32/64 Table 3-7.
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AT32UC3L016/32/64 Table 3-7. Signal Descriptions List CLK Clock CTS Clear To Send RTS Request To Send RXD Receive Data Input TXD Transmit Data Output Note: I/O Input Low Output Low 1. ADCIFB: AD3 does not exist. Table 3-8. Signal Description List, Continued Signal Name Function Type Active Level Comments Power VDDCORE Core Power Supply / Voltage Regulator Output Power Input/Output 1.62V to 1.98V VDDIO I/O Power Supply Power Input 1.62V to 3.6V.
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AT32UC3L016/32/64 3.4 3.4.1 I/O Line Considerations JTAG Pins The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI pins have pull-up resistors when JTAG is enabled. The TCK pin always has pull-up enabled during reset. The TDO pin is an output, driven at VDDIO, and has no pull-up resistor. The JTAG pins can be used as GPIO pins and multiplexed with peripherals when the JTAG is disabled. Please refer to Section 3.2.3 on page 11 for the JTAG port connections. 3.4.
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AT32UC3L016/32/64 3.4.8 RC32OUT Pin 3.4.8.1 Clock output at startup After power-up, the clock generated by the 32kHz RC oscillator (RC32K) will be output on PA20, even when the device is still reset by the Power-On Reset Circuitry. This clock can be used by the system to start other devices or to clock a switching regulator to rise the power supply voltage up to an acceptable value.
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AT32UC3L016/32/64 4. Processor and Architecture Rev: 2.1.0.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 4.
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AT32UC3L016/32/64 single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 4.
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AT32UC3L016/32/64 OCD interface Reset interface Overview of the AVR32UC CPU Interrupt controller interface Figure 4-1. OCD system Power/ Reset control AVR32UC CPU pipeline MPU 4.3.
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AT32UC3L016/32/64 Figure 4-2. The AVR32UC Pipeline MUL IF ID Prefetch unit Decode unit Regfile Read ALU LS 4.3.2 Multiply unit Regfile write ALU unit Load-store unit AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts.
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AT32UC3L016/32/64 address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. 4.3.2.5 Instructions with Unaligned Reference Support Instruction Supported Alignment ld.d Word st.
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AT32UC3L016/32/64 4.4 4.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 4-3.
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AT32UC3L016/32/64 Figure 4-5. The Status Register Low Halfword Bit 15 Bit 0 - T - - - - - - - - L Q V N Z C Bit name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 4.4.3 Processor States 4.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2. Table 4-2. Overview of Execution Modes, their Priorities and Privilege Levels.
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AT32UC3L016/32/64 Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 4.4.4 Secure State The AVR32 can be set in a secure state, that allows a part of the code to execute in a state with higher security levels. The rest of the code can not access resources reserved for this secure code. Secure State is used to implement FlashVault technology. Refer to the AVR32UC Technical Reference Manual for details.
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AT32UC3L016/32/64 Table 4-3.
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AT32UC3L016/32/64 Table 4-3. 4.
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AT32UC3L016/32/64 relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up appropriately. The same mechanisms are used to service all different types of events, including interrupt requests, yielding a uniform event handling scheme.
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AT32UC3L016/32/64 4.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from timecritical event handlers.
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AT32UC3L016/32/64 than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 4-4 on page 31. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floatingpoint unit.
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AT32UC3L016/32/64 Table 4-4.
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AT32UC3L016/32/64 5. Memories 5.
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AT32UC3L016/32/64 5.3 Peripheral Address Map Table 5-3.
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AT32UC3L016/32/64 Table 5-3.
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AT32UC3L016/32/64 The following GPIO registers are mapped on the local bus: Table 5-4.
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AT32UC3L016/32/64 6. Supply and Startup Considerations 6.1 6.1.1 Supply Considerations Power Supplies The AT32UC3L016/32/64 has several types of power supply pins: •VDDIO: Powers I/O lines. Voltage is 1.8 to 3.3V nominal. •VDDIN: Powers I/O lines and the internal regulator. Voltage is 1.8 to 3.3V nominal. •VDDANA: Powers the ADC. Voltage is 1.8V nominal. •VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal. The ground pins GND are common to VDDCORE, VDDIO, and VDDIN.
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AT32UC3L016/32/64 6.1.3.1 3.3V Single Supply Mode In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin) and its output feeds VDDCORE. Figure 6-2 shows the power schematics to be used for 3.3V single supply mode. All I/O lines will be powered by the same power (VDDIN=VDDIO). Figure 6-2. 3.3V Single Supply Mode + 1.98-3.
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AT32UC3L016/32/64 6.1.3.2 1.8V Single Supply Mode In 1.8V single supply mode the internal regulator is not used, and VDDIO and VDDCORE are powered by a single 1.8V supply as shown in Figure 6-3. All I/O lines will be powered by the same power (VDDIN = VDDIO = VDDCORE). Figure 6-3. 1.8V Single Supply Mode. + 1.62-1.
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AT32UC3L016/32/64 6.1.3.3 3.3V Supply Mode with 1.8V Regulated I/O Lines In this mode, the internal regulator is connected to the 3.3V source and its output is connected to both VDDCORE and VDDIO as shown in Figure 6-4. This configuration is required in order to use Shutdown mode. Figure 6-4. 3.3V Supply Mode with 1.8V Regulated I/O Lines 1.98-3.
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AT32UC3L016/32/64 6.1.4 Power-up Sequence 6.1.4.1 Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Table 7-3 on page 42. Recommended order for power supplies is also described in this chapter. 6.1.4.2 Minimum Rise Rate The integrated Power-on Reset (POR33) circuitry monitoring the VDDIN powering supply requires a minimum rise rate for the VDDIN power supply. See Table 7-3 on page 42 for the minimum rise rate value.
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AT32UC3L016/32/64 7. Electrical Characteristics 7.1 Absolute Maximum Ratings* Table 7-1. Absolute Maximum Ratings Operating temperature..................................... -40°C to +85°C *NOTICE: Storage temperature...................................... -60°C to +150°C Voltage on input pins (except for 5V pins) with respect to ground .................................................................-0.3V to VVDD(2)+0.3V Voltage on 5V tolerant(1) pins with respect to ground ............... ............
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AT32UC3L016/32/64 Table 7-3. Supply Rise Rates and Order(1) Rise Rate Symbol Parameter Min Max Unit VVDDIO DC supply peripheral I/Os 0 2.5 V/µs VVDDIN DC supply peripheral I/Os and internal regulator 0.002 2.5 V/µs Slower rise time requires external power-on reset circuit. VVDDCORE DC supply core 0 2.5 V/µs Rise before or at the same time as VDDIO VVDDANA Analog supply voltage 0 2.5 V/µs Rise together with VDDCORE Note: 7.3 Comment 1.
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AT32UC3L016/32/64 – Corresponds to the 3.3V supply mode with 1.8V regulated I/O lines, please refer to the Supply and Startup Considerations section for more details • Equivalent to the 3.3V single supply mode • Consumption in 1.8V single supply mode can be estimated by subtracting the regulator static current • Operating conditions external core supply (Figure 7-2) - used only when noted – VVDDIN = VVDDCORE = 1.8V – Corresponds to the 1.
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AT32UC3L016/32/64 Table 7-5. Mode Power Consumption for Different Operating Modes Conditions Active(1) Measured on Consumption Typ -CPU running a recursive Fibonacci algorithm 260 -CPU running a division algorithm 165 Idle(1) 92 (1) (1) 47 Stop 37 DeepStop 23 -OSC32K and AST stopped -Internal core supply Static Shutdown Amp0 10 µA -OSC32K running -AST running at 1KHz -External core supply (Figure 7-2) 5.3 -OSC32K and AST stopped -External core supply (Figure 7-2) 4.
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AT32UC3L016/32/64 Figure 7-2. Measurement Schematic, External Core Supply Amp0 VDDIN VDDIO VDDCORE VDDANA 7.4.1 Peripheral Power Consumption The values in Table 7-6 are measured values of power consumption under the following conditions. • Operating conditions internal core supply (Figure 7-1) – VVDDIN = 3.0V – VVDDCORE = 1.62V, supplied by the internal regulator – Corresponds to the 3.3V supply mode with 1.
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AT32UC3L016/32/64 Table 7-6. Peripheral Typical Current Consumption by Peripheral(2) Typ Consumption Active ACIFB 14.0 ADCIFB(1) 14.9 AST 5.6 AW USART 6.8 CAT 12.4 EIC 1.3 FREQM 3.2 GLOC 0.4 GPIO 15.9 PWMA 2.5 SPI 7.6 TC 7.2 TWIM 5.1 TWIS 3.2 USART 12.3 WDT 2.3 Unit µA/MHz Notes: 1. Includes the current consumption on VDDANA and ADVREFP. 2. These numbers are valid for the measured condition only and must not be extrapolated to other frequencies.
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AT32UC3L016/32/64 7.5 I/O Pin Characteristics Table 7-7. Normal I/O Pin Characteristics(1) Symbol Parameter RPULLUP Pull-up resistance VIL Input low-level voltage VIH Input high-level voltage VOL Output low-level voltage VOH Output high-level voltage fMAX Output frequency(2) tRISE Rise time(2) Condition Min Typ Max Units 75 100 145 kOhm VVDD = 3.0V -0.3 0.3*VVDD VVDD = 1.62V -0.3 0.3*VVDD VVDD = 3.6V 0.7*VVDD VVDD + 0.3 VVDD = 1.98V 0.7*VVDD VVDD + 0.3 VVDD = 3.
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AT32UC3L016/32/64 Table 7-8. High-drive I/O Pin Characteristics(1) Symbol Parameter Condition Min Typ Max VIL Input low-level voltage VVDD = 3.0V -0.3 0.3*VVDD VVDD = 1.62V -0.3 0.3*VVDD VIH Input high-level voltage VVDD = 3.6V 0.7*VVDD VVDD + 0.3 VVDD = 1.98V 0.7*VVDD VVDD + 0.3 VOL Output low-level voltage VOH Output high-level voltage Output frequency, all Highdrive I/O pins, except PA08 and PA09(2) VVDD = 3.0V, load = 10pF 45 fMAX VVDD = 3.
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AT32UC3L016/32/64 Table 7-9. High-drive I/O, 5V Tolerant, Pin Characteristics(1) Symbol Parameter VIH Input high-level voltage VOL Output low-level voltage VOH Output high-level voltage fMAX Output frequency(2) tRISE Rise time(2) (2) tFALL Fall time ILEAK Input leakage current CIN Notes: Input capacitance Condition Min Typ Max VVDD = 3.6V 0.7*VVDD 5.5 VVDD = 1.98V 0.7*VVDD 5.5 Units V VVDD = 3.0V, IOL = 6mA 0.4 VVDD = 1.62V, IOL = 4mA 0.4 V VVDD = 3.
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AT32UC3L016/32/64 Table 7-10. TWI Pin Characteristics(1) Symbol Parameter tFALL Fall time fMAX Max frequency Condition Min Typ Cbus = 400pF, VVDD > 2.0V 250 Cbus = 400pF, VVDD > 1.62V 470 Cbus = 400pF, VVDD > 2.0V Max Units ns 400 kHz Note: 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section 3.2 on page 9 for details. 7.6 Oscillator Characteristics 7.6.1 Oscillator 0 (OSC0) Characteristics 7.6.1.
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AT32UC3L016/32/64 Table 7-12. Symbol Crystal Oscillator Characteristics Parameter tSTARTUP Conditions Min (1) Startup time SCIF.OSCCTRL.GAIN = 2 Current consumption Notes: Max (2) 30 000 Active mode, f = 0.45MHz, SCIF.OSCCTRL.GAIN = 0 IOSC Typ Unit cycles 30 µA Active mode, f = 10MHz, SCIF.OSCCTRL.GAIN = 2 170 1. Please refer to the SCIF chapter for details. 2. Nominal crystal cycles. 3.
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AT32UC3L016/32/64 Notes: 1. Nominal crystal cycles. 2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. 7.6.3 Digital Frequency Locked Loop (DFLL) Characteristics Table 7-14.
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AT32UC3L016/32/64 Figure 7-4. DFLL Open Loop Frequency Variation(1) DFLL Open Loop Frequency variation 160 150 Frequencies (MHz) 140 130 1,98V 120 1,8V 1.62V 110 100 90 80 -40 -20 0 20 40 60 80 Tem pera ture Note: 1. The plot shows a typical behaviour for coarse = 99 and fine = 255 in open loop mode. 7.6.4 120MHz RC Oscillator (RC120M) Characteristics Table 7-15.
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AT32UC3L016/32/64 7.6.5 32kHz RC Oscillator (RC32K) Characteristics Table 7-16. Symbol 32kHz RC Oscillator Characteristics Parameter Conditions (1) Min Typ Max Unit 20 32 44 kHz fOUT Output frequency IRC32K Current consumption 0.6 µA tSTARTUP Startup time 100 µs Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. 7.6.
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AT32UC3L016/32/64 Table 7-20. Flash Endurance and Data Retention Symbol Parameter NFARRAY Array endurance (write/page) 100k NFFUSE General Purpose fuses endurance (write/bit) 10k tRET Data retention 15 7.8 Min Typ Max Unit cycles years Analog Characteristics 7.8.1 Voltage Regulator Characteristics Table 7-21. VREG Electrical Characteristics Symbol Parameter VVDDIN Input voltage range VVDDCORE Output voltage, calibrated value Condition Min Typ Max 1.98 3.3 3.
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AT32UC3L016/32/64 7.8.2 Power-on Reset 18 Characteristics Table 7-23. POR18 Characteristics Symbol Parameter Condition VPOT+ Voltage threshold on VVDDCORE rising VPOT- Voltage threshold on VVDDCORE falling tDET Detection time Typ Max 1.45 1.58 Units V 1.2 Time with VDDCORE < VPOTnecessary to generate a reset signal 1.32 460 µs POR18 Operating Principles VVDDCORE Figure 7-5.
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AT32UC3L016/32/64 7.8.3 Power-on Reset 33 Characteristics Table 7-24. POR33 Characteristics Symbol Parameter Condition VPOT+ Voltage threshold on VVDDIN rising VPOT- Voltage threshold on VVDDIN falling tDET Detection time Time with VDDIN < VPOTnecessary to generate a reset signal 460 µs IPOR33 Current consumption After tRESET 15 µA tSTARTUP Startup time 400 µs Typ Max 1.49 1.58 Units V 1.3 1.45 POR33 Operating Principles VVDDIN Figure 7-6. Min Reset VPOT+ VPOT- 7.8.
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AT32UC3L016/32/64 Table 7-26. BOD Characteristics Symbol Parameter Condition VHYST BOD hysteresis T = 25°C 10 mV tDET Detection time Time with VDDCORE < BODLEVEL necessary to generate a reset signal 1 µs IBOD Current consumption 16 µA tSTARTUP Startup time 5 µs 7.8.5 Min Typ Max Units Supply Monitor 33 Characteristics Table 7-27. Symbol VTH SM33 Characteristics Parameter Voltage threshold Condition (1) Calibrated , T = 25°C Min Typ Max Units 1.675 1.75 1.
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AT32UC3L016/32/64 7.8.6 Analog to Digital Converter Characteristics Table 7-28. ADC Characteristics Symbol Parameter Conditions fADC ADC clock frequency tSTARTUP Startup time Return from Idle Mode tCONV Conversion time (latency) fADC = 6MHz Throughput rate Min Typ 10-bit resolution mode 6 8-bit resolution mode 6 15 11 VVDD > 3.0V, fADC = 6MHz, 10-bit resolution mode, low impedance source 460 VVDD > 3.
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AT32UC3L016/32/64 Figure 7-7. ADC Input RSOURCE Positive Input RONCHIP CSOURCE VIN CONCHIP ADCVREFP/2 The minimum sample and hold time (in ns) can be found using this formula: t SAMPLEHOLD ≥ ( R ONCHIP + R OFFCHIP ) × ( C ONCHIP + C OFFCHIP ) × ln ( 2 n+1 ) Where n is the number of bits in the conversion. t SAMPLEHOLD is defined by the SHTIM field in the ADCIFB ACR register. Please refer to the ADCIFB chapter for more information. 7.8.6.2 Table 7-30.
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AT32UC3L016/32/64 7.8.7 Temperature Sensor Characteristics Temperature Sensor Characteristics(1) Table 7-32. Symbol Parameter Condition Min Typ Max Units Gradient 1 mV/°C ITS Current consumption 0.5 µA tSTARTUP Startup time 0 µs Note: 1. The Temperature Sensor is not calibrated. The accuracy of the Temperature Sensor is governed by the ADC accuracy. 7.8.8 Analog Comparator Characteristics Table 7-33.
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AT32UC3L016/32/64 7.8.9 Capacitive Touch Characteristics 7.8.9.1 Table 7-34. Discharge Current Source DICS Characteristics Symbol Parameter RREF Internal resistor 120 kOhm k Trim step size 0.7 % 7.8.9.2 Table 7-35.
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AT32UC3L016/32/64 7.9 Timing Characteristics 7.9.1 Startup, Reset, and Wake-up Timing The startup, reset, and wake-up timings are calculated using the following formula: t = t CONST + N CPU × t CPU Where t CONST and N CPU are found in Table 7-36. t CPU is the period of the CPU clock. If another clock source than RCSYS is selected as CPU clock the startup time of the oscillator, t OSCSTART , must added to the wake-up time in the stop, deepstop, and static sleep modes.
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AT32UC3L016/32/64 7.9.3 USART in SPI Mode Timing 7.9.3.1 Master mode Figure 7-8. USART in SPI Master Mode With (CPOL= CPHA= 0) or (CPOL= CPHA= 1) SPCK MISO USPI0 USPI1 MOSI USPI2 Figure 7-9. USART in SPI Master Mode With (CPOL= 0 and CPHA= 1) or (CPOL= 1 and CPHA= 0) SPCK MISO USPI3 USPI4 MOSI USPI5 Table 7-38.
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AT32UC3L016/32/64 Maximum SPI Frequency, Master Output The maximum SPI master output frequency is given by the following formula: 1 f CLKSPI × 2 f SPCKMAX = MIN (f PINMAX,------------, -----------------------------) SPIn 9 Where SPIn is the MOSI delay, USPI2 or USPI5 depending on CPOL and NCPHA. f PINMAX is the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the maximum frequency of the pins. f CLKSPI is the maximum frequency of the CLK_SPI.
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AT32UC3L016/32/64 Figure 7-12. USART in SPI Slave Mode NPCS Timing USPI12 USPI13 USPI14 USPI15 SPCK, CPOL=0 SPCK, CPOL=1 NSS Table 7-39. USART in SPI mode Timing, Slave Mode(1) Symbol Parameter Conditions USPI6 SPCK falling to MISO delay Max Units 27.
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AT32UC3L016/32/64 The maximum SPI slave output frequency is given by the following formula: f CLKSPI × 2 1 f SPCKMAX = MIN (-----------------------------, f PINMAX,------------------------------------) 9 SPIn + t SETUP Where SPIn is the MISO delay, USPI6 or USPI9 depending on CPOL and NCPHA. T SETUP is the SPI master setup time. Please refer to the SPI master datasheet for T SETUP . f CLKSPI is the maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this clock.
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AT32UC3L016/32/64 Table 7-40. SPI Timing, Master Mode(1) Symbol Parameter SPI0 MISO setup time before SPCK rises SPI1 MISO hold time after SPCK rises SPI2 SPCK rising to MOSI delay SPI3 MISO setup time before SPCK falls SPI4 MISO hold time after SPCK falls SPI5 SPCK falling to MOSI delay Note: Conditions Min Max Units 28.4 + (tCLK_SPI)/2 VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF 0 7.1 ns 22.8 + (tCLK_SPI)/2 0 11.0 1.
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AT32UC3L016/32/64 Figure 7-16. SPI Slave Mode With (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1) SPCK MISO SPI9 MOSI SPI10 Figure 7-17. SPI11 SPI Slave Mode NPCS Timing SPI12 SPI13 SPI14 SPI15 SPCK, CPOL=0 SPCK, CPOL=1 NPCS Table 7-41.
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AT32UC3L016/32/64 The maximum SPI slave input frequency is given by the following formula: 1 f SPCKMAX = MIN (f CLKSPI,------------) SPIn Where SPIn is the MOSI setup and hold time, SPI7 + SPI8 or SPI10 + SPI11 depending on CPOL and NCPHA. f CLKSPI is the maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this clock.
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AT32UC3L016/32/64 Table 7-42. TWI-Bus Timing Requirements Minimum Symbol Parameter tSU-DAT-TWI Data set-up time tSU-DAT tLOW-TWI Mode Requirement Standard 250 Fast 100 - Device - Standard 4.7 Fast 1.3 TWCK LOW period tLOW - tHIGH TWCK HIGH period fTWCK TWCK frequency - Standard 4.0 Fast 0.6 Standard Notes: Maximum Requirement Unit 2tclkpb - ns tclkpb - - 4tclkpb - μs tclkpb - - 8tclkpb - μs 100 - Fast Device 400 1 -----------------------12t clkpb kHz 1.
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AT32UC3L016/32/64 7.9.6 JTAG Timing Figure 7-18. JTAG Interface Signals JTAG2 TCK JTAG0 JTAG1 TMS/TDI JTAG3 JTAG4 JTAG7 JTAG8 TDO JTAG5 JTAG6 Boundary Scan Inputs Boundary Scan Outputs JTAG9 JTAG10 Table 7-43. JTAG Timings(1) Symbol Parameter JTAG0 TCK Low Half-period 23.2 JTAG1 TCK High Half-period 8.8 JTAG2 TCK Period 32.
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AT32UC3L016/32/64 8. Mechanical Characteristics 8.1 8.1.1 Thermal Considerations Thermal Data Table 8-1 summarizes the thermal resistance data depending on the package. Table 8-1. 8.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ θJA Junction-to-ambient thermal resistance Still Air TQFP48 63.2 θJC Junction-to-case thermal resistance TQFP48 21.8 θJA Junction-to-ambient thermal resistance QFN48 28.3 θJC Junction-to-case thermal resistance QFN48 2.
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AT32UC3L016/32/64 8.2 Package Drawings Figure 8-1. TQFP-48 Package Drawing Table 8-2. Device and Package Maximum Weight 140 Table 8-3. mg Package Characteristics Moisture Sensitivity Level Table 8-4.
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AT32UC3L016/32/64 Figure 8-2. Note: QFN-48 Package Drawing The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 8-5. Device and Package Maximum Weight 140 Table 8-6. mg Package Characteristics Moisture Sensitivity Level Table 8-7.
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AT32UC3L016/32/64 Figure 8-3. TLLGA-48 Package Drawing Table 8-8. Device and Package Maximum Weight 39.3 Table 8-9. mg Package Characteristics Moisture Sensitivity Level Table 8-10.
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AT32UC3L016/32/64 8.3 Soldering Profile Table 8-11 gives the recommended soldering profile from J-STD-20. Table 8-11.
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AT32UC3L016/32/64 9. Ordering Information Table 9-1.
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AT32UC3L016/32/64 10. Errata 10.1 10.1.1 Rev. E Processor and Architecture 1. Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions. 2. Privilege violation when using interrupts in application mode with protected system stack If the system stack is protected by the MPU and an interrupt occurs in application mode, an MPU DTLB exception will occur.
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AT32UC3L016/32/64 If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walking, all PB clocks will be masked except the PB clock to the sleepwalking module. Fix/Workaround Mask all clock requests in the PM.PPCR register before going into idle or frozen mode. 10.1.4 SCIF 1. PCLKSR.OSC32RDY bit might not be cleared after disabling OSC32K In some cases the OSC32RDY bit in the PCLKSR register will not be cleared when OSC32K is disabled.
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AT32UC3L016/32/64 Use twice as long timeout period as needed and clear the WDT counter within the first half of the timeout period. If the WDT counter is cleared after the first half of the timeout period, you will get a Watchdog reset immediately. If the WDT counter is not cleared at all, the time before the reset will be twice as long as needed. 2.
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AT32UC3L016/32/64 Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. 5. SPI mode fault detection enable causes incorrect behavior When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate properly. Fix/Workaround Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS. 10.1.9 TWI 1. TWIM SR.
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AT32UC3L016/32/64 6. TWIS stretch on Address match error When the TWIS stretches TWCK due to a slave address match, it also holds TWD low for the same duration if it is to be receiving data. When TWIS releases TWCK, it releases TWD at the same time. This can cause a TWI timing violation. Fix/Workaround None. 10.1.10 PWMA 1. BUSY bit is never cleared after writes to the Control Register (CR) When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR when the PWMA is disabled (CR.
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AT32UC3L016/32/64 The CAT module does not terminate a QTouch burst when the detection voltage is reached on the sense capacitor. This can cause the sense capacitor to be charged more than necessary. Depending on the dielectric absorption characteristics of the capacitor, this can lead to unstable measurements. Fix/Workaround Use the minimum possible value for the MAX field in the ATCFG1, TG0CFG1, and TG1CFG1 registers. 4.
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AT32UC3L016/32/64 10.2 10.2.1 Rev. D Processor and Architecture 1. Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions. 2. Privilege violation when using interrupts in application mode with protected system stack If the system stack is protected by the MPU and an interrupt occurs in application mode, an MPU DTLB exception will occur.
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AT32UC3L016/32/64 - When entering Shutdown mode while debugging the chip using JTAG or aWire interface In the listed cases, writing a one to the bit VREGCR.POR33MASK in the System Control Interface (SCIF) to mask the POR33 reset will be ineffective Fix/Workaround - Do not disable POR33 using the user interface - Do not use the SM33 supply monitor - Do not enter Shutdown mode if a debugger is connected to the chip 4.
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AT32UC3L016/32/64 - Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as zero. 10.2.5 AST 1. Reset may set status bits in the AST If a reset occurs and the AST is enabled, the SR.ALARM0, SR.PER0, and SR.OVF bits may be set. Fix/Workaround If the part is reset and the AST is used, clear all bits in the Status Register before entering sleep mode. 2.
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AT32UC3L016/32/64 10.2.8 SPI 1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. 2. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE.
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AT32UC3L016/32/64 The TWALM signal in the TWIM is active high instead of active low. Fix/Workaround Use an external inverter to invert the signal going into the TWIM. When using both TWIM and TWIS on the same pins, the TWALM cannot be used. 3. TWIS may not wake the device from sleep mode If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condition, the CPU may not wake upon a TWIS address match. The request is NACKed.
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AT32UC3L016/32/64 10.2.11 ADCIFB 1. Using STARTUPTIME larger than 0x1F will freeze the ADC Writing a value larger than 0x1F to the Startup Time field in the ADC Configuration Register (ACR.STARTUP) will freeze the ADC, and the Busy Status bit in the Status Register (SR.BUSY) will never be cleared. Fix/Workaround Do not write values larger than 0x1F to ACR.STARTUP. 10.2.12 CAT 1.
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AT32UC3L016/32/64 None. 2. The aWire debug interface is reset after leaving Shutdown mode If the aWire debug mode is used as debug interface and the program enters Shutdown mode, the aWire interface will be reset when the part receives a wakeup either from the WAKE_N pin or the AST. Fix/Workaround None. 10.2.14 CHIP 1. In 3.3V Single Supply Mode, the Analog Comparator inputs affects the device’s ability to start When using the 3.
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AT32UC3L016/32/64 atomically. Even if this step is generally described as not safe in the UC technical reference manual, it is safe in this very specific case. 2. Execute the RETE instruction. 2. Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions. 3.
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AT32UC3L016/32/64 Fix/Workaround Solution 1: Make sure that the appropriate instructions are executed from RAM, and that a waiting-loop is executed from RAM waiting 500ns or more before executing from flash. Solution 2. Execute from flash with a clock with period longer than 500ns. This guarantees that no new read access is attempted before the flash has had time to settle in the new read mode. 4.
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AT32UC3L016/32/64 2. It is not possible to mask the request clock requests It is not possible to mask the request clock requests using PPCR. Fix/Workaround None. 3. Static mode cannot be entered if the WDT is using OSC32 If the WDT is using OSC32 as clock source and the user tries to enter Static mode, the Deepstop mode will be entered instead. Fix/Workaround None. 4. Clock Failure Detector (CFD) does not work Clock Failure Detector (CFD) does not work. Fix/Workaround None. 5.
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AT32UC3L016/32/64 - The OSC0 is enabled in external clock mode (OSCCTRL0.OSCEN == 1 and OSCCTRL0.MODE == 0) - A sleep mode where the OSC0 is automatically disabled is entered - The device enters sleep walking Fix/Workaround Do not run OSC0 in external clock mode if sleepwalking is expected to be used. 10.
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AT32UC3L016/32/64 Fix/Workaround If the target frequency is below 30MHz, use a max step size (DFLL0MAXSTEP.MAXSTEP) of seven or lower. 7. Generic clock sources are kept running in sleep modes If a clock is used as a source for a generic clock when going to a sleep mode where clock sources are stopped, the source of the generic clock will be kept running. Please refer to Power Manager chapter for details about sleep modes.
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AT32UC3L016/32/64 15. BODVERSION register reads 0x100 BODVERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 16. DFLLVERSION register reads 0x200 DFLLVERSION register reads 0x200 instead of 0x201. Fix/Workaround None. 17. RCCRVERSION register reads 0x100 RCCRVERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 18. OSC32VERSION register reads 0x100 OSC32VERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 19.
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AT32UC3L016/32/64 Fix/Workaround Use twice as long timeout period as needed and clear the WDT counter within the first half of the timeout period. If the WDT counter is cleared after the first half of the timeout period, you will get a Watchdog reset immediately. If the WDT counter is not cleared at all, the time before the reset will be twice as long as needed. 3. VERSION register reads 0x400 The VERSION register reads 0x400 instead of 0x402. Fix/Workaround None. 4.
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AT32UC3L016/32/64 The RTS signal is not generated properly when the USART receives data in hardware handshaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output should go high, but it will stay low. Fix/Workaround Do not use the hardware handshaking mode of the USART. If it is necessary to drive the RTS output high when the Peripheral DMA receive buffer becomes full, use the normal mode of the USART.
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AT32UC3L016/32/64 The TWI pins draw current when they are supplied with 3.3V and the part is left unpowered. Fix/Workaround None. 2. PA21, PB04, and PB05 are not 5V tolerant Pins PA21, PB04, and PB05 are only 3.3V tolerant. Fix/Workaround None. 3. PB04 SMBALERT function should not be used The SMBALERT function from TWIMS0 should not be selected on pin PB04. Fix/Workaround None. 4. TWIM STOP bit in IMR always reads as zero The STOP bit in IMR always reads as zero. Fix/Workaround None. 5.
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AT32UC3L016/32/64 Fix/Workaround Use TWI0.TWCK on other pins. 10. TWIM Version Register reads zero TWIM Version Register (VR) reads zero instead of 0x101 Fix/Workaround None. 11. TWIS Version Register reads zero TWIS Version Register (VR) reads zero instead of 0x112 Fix/Workaround None. 12. SMBALERT bit may be set after reset The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after system reset. Fix/Workaround After system reset, clear the SR.
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AT32UC3L016/32/64 4. BUSY bit is never cleared after writes to the Control Register (CR) When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR when the PWMA is disabled (CR.EN == 0), the BUSY bit in the Status Register (SR.BUSY) will be set, but never cleared. Fix/Workaround When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR, make sure the PWMA is enabled, or simultaneously enable the PWMA by writing a one to CR.EN. 5.
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AT32UC3L016/32/64 The VERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 10.4.18 ACIFB 1. Generic clock sources in sleep modes. The ACIFB should not use RC32K or CLK_1K as generic clock source if the chip uses sleep modes. Fix/Workaround None. 2. Negative offset The static offset of the analog comparator is approximately -50mV Fix/Workaround None. 3. CONFW.WEVSRC and CONFW.WEVEN are not correctly described in the user interface CONFW.WEVSRC is only two bits instead of three bits wide.
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AT32UC3L016/32/64 Fix/Workaround None. 5. MGCFG2.ACCTRL bit is stuck at zero The ACCTRL bit in the MGCFG2 register is stuck at zero and cannot be written to one. The analog comparators will be constantly enabled. Fix/Workaround None. 6. CAT asynchronous wake will be delayed by one AST event period If the CAT detects a condition the should asynchronously wake the device in static mode, the asynchronous wake will not occur until the next AST event.
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AT32UC3L016/32/64 2. If a reset happens during the last SAB write, the aWire will stall If a reset happens during the last word, halfword or byte write the aWire will wait forever for an acknowledge from the SAB. Fix/Workaround Reset the aWire by keeping the RESET_N line low for 100ms. 3. aWire enable does not work in Static mode aWire enable does not work in Static mode. Fix/Workaround None. 4.
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AT32UC3L016/32/64 When VDDIN increases above 1.8V, current on VDDIN increases with up to 40uA. Fix/Workaround None. 5. Increased Power Consumption in VDDIO in sleep modes If OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is disabled, this will lead to an increased power consumption in VDDIO. Fix/Workaround Solution 1: Disable OSC0 by writing a zero to the Oscillator Enable bit in the System Control Interface (SCIF) Oscillator Control Register (SCIF.OSC0CTRL.
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AT32UC3L016/32/64 11. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 11.2 Rev. I - 01/2012 1. Overview - Block diagram: CAT SMP corrected from I/O to output. SPI NPCS corrected from output to I/O. 2. Package and Pinout: PRND signal removed from Signal Descriptions List table and GPIO Controller Function Multiplexing table 3.
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AT32UC3L016/32/64 11.3 11.4 11.5 15. Electrcal Characteristics: Updated SPI timing data. 16. Electrical Characteristics, I/O Pin Characteristics: Added Input capacitance for TLLGA48 package. 17. Errata: Removed erratum regarding SPI RDR.PCS field, as the PCS field has been removed (refer to Section 11.8 on page 109). Rev. G - 06/2011 1. FLASHCDW: FSR register is a Read-only register. Added info about QPRUP. 2. PM: Clarified POR33 masking requirements before shutdown.
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AT32UC3L016/32/64 11.6 11. ADCIFB: Fixed Sample and Hold time formula. 12. GLOC: Added info about pullup control and renamed LUTCR register to CR. 13. TC: Added features and version register. 14. SAU: Added OPEN bit to config register. Added description of unlock fields. 15. TWIS: SCR is Write-only. Improved explanation of slave transmitter mode. Updated data transfer diagrams. 16. Electrical Characteristics: Added more values. Added notes on simulated and characterized values.
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AT32UC3L016/32/64 11.9 11. PM: Entering Shutdown mode description updated. 12. SCIF: DFLL output frequency is 40-150MHz, not 20-150MHz or 30-150MHz. 13. SCIF: Temperature sensor is connected to ADC channel 9, not 7. 14. SCIF: Updated the oscillator connection figure for OSC0 15. GPIO: Removed unimplemented features (pull-down, buskeeper, drive strength, slew rate, Schmidt trigger, open drain). 16. SPI: RDR.PCS field removed (RDR[19:16]). 17. TWIS: Figures updated. 18.
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AT32UC3L016/32/64 Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 4 5 6 7 2.1 Block Diagram ...................................................................................................
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AT32UC3L016/32/64 8 9 7.8 Analog Characteristics .....................................................................................55 7.9 Timing Characteristics .....................................................................................63 Mechanical Characteristics ................................................................... 73 8.1 Thermal Considerations ..................................................................................73 8.2 Package Drawings ...................
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 16F, Shin Osaki Kangyo Bldg.