Datasheet

8
32145CS–06/2013
AT32UC3L0128/256
Figure 3-2. TLLGA48 Pinout
3.2 Peripheral Multiplexing on I/O Lines
3.2.1 Multiplexed Signals
Each GPIO line can be assigned to one of the peripheral functions. The following table
describes the peripheral signals multiplexed to the GPIO lines.
GND1 PA09
2
PA08
3
PA03
4
PB12
5
PB00
6
PB02
7
PB03
8
PA22
9
PA06
10
PA00
11
PA05
12
PA02
13
PA0114
PA0715
PB0116
VDDIN17
VDDCORE18
GND19
PB0520
PB0421
RESET_N22
PB1023
PA2124
PA1436 VDDANA35 ADVREFP
34
GNDANA33 PB0832 PB0731 PB0630 PB0929 PA0428 PA1127 PA1326 PA2025
PA15
37
PA16 38
PA17 39
PA19 40
PA18 41
VDDIO 42
GND 43
PB11 44
GND 45
PA10 46
PA12 47
VDDIO 48
Table 3-1. GPIO Controller Function Multiplexing
48-
pin PIN
G
P
I
O Supply
Pin
Type
GPIO Function
AB C D E F GH
11 PA00 0 VDDIO
Normal
I/O
U S A R T 0
TXD
U S A R T 1
RTS
SP I
NPCS[2]
P W M A
PWMA[0]
S C I F
GCLK[0]
C AT
CSA[2]
14 PA01 1 VDDIO
Normal
I/O
U S A R T 0
RXD
U S A R T 1
CTS
SP I
NPCS[3]
U S A R T 1
CLK
P W M A
PWMA[1]
A CI FB
ACAP[0]
T W I M S 0
TWALM
C AT
CSA[1]