Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 48 (7x7) 32-Bit 50 MHz I/O number 36

Features

• High-performance, Low-power 32-bit Atmel

AVR

Microcontroller

– Compact Single-cycle RISC Instruction Set Including DSP Instructions

– Read-modify-write Instructions and Atomic Bit Manipulation

– Performance

• Up to 64DMIPS Running at 50MHz from Flash (1 Flash Wait State)

• Up to 36DMIPS Running at 25MHz from Flash (0 Flash Wait State)

– Memory Protection Unit (MPU)

• Secure Access Unit (SAU) providing User-defined Peripheral Protection

• picoPower

Technology for Ultra-low Power Consumption

• Multi-hierarchy Bus System

– High-performance Data Transfers on Separate Buses for Increased Performance

– 12 Peripheral DMA Channels Improve Speed for Peripheral Communication

• Internal High-speed Flash

– 256Kbytes and 128Kbytes Versions

– Single-cycle Access up to 25MHz

– FlashVault Technology Allows Pre-programmed Secure Library Support for End

User Applications

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 100,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User-defined Configuration Area

• Internal High-speed SRAM, Single-cycle Access at Full Speed

–32Kbytes

• Interrupt Controller (INTC)

– Autovectored Low-latency Interrupt Service with Programmable Priority

• External Interrupt Controller (EIC)

• Peripheral Event System for Direct Peripheral to Peripheral Communication

• System Functions

– Power and Clock Manager

– SleepWalking Power Saving Control

– Internal System RC Oscillator (RCSYS)

– 32 KHz Oscillator

– Multipurpose Oscillator, Phase Locked Loop (PLL), and Digital Frequency Locked

Loop (DFLL)

• Windowed Watchdog Timer (WDT)

• Asynchronous Timer (AST) with Real-time Clock Capability

– Counter or Calendar Mode Supported

• Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency

• Six 16-bit Timer/Counter (TC) Channels

– External Clock Inputs, PWM, Capture, and Various Counting Capabilities

• PWM Channels on All I/O Pins (PWMA)

– 8-bit PWM with a Source Clock up to 150MHz

• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– Independent Baudrate Generator, Support for SPI

– Support for Hardware Handshaking

• One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals

– Up to 15 SPI Slaves can be Addressed

32145CS–06/2013

32-bit Atmel

AVR

Microcontroller

AT32UC3L0256

AT32UC3L0128

Summary

Summary of content (39 pages)

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Features • High-performance, Low-power 32-bit Atmel® AVR® Microcontroller • • • • • • • • • • • • • • • – Compact Single-cycle RISC Instruction Set Including DSP Instructions – Read-modify-write Instructions and Atomic Bit Manipulation – Performance • Up to 64DMIPS Running at 50MHz from Flash (1 Flash Wait State) • Up to 36DMIPS Running at 25MHz from Flash (0 Flash Wait State) – Memory Protection Unit (MPU) • Secure Access Unit (SAU) providing User-defined Peripheral Protection picoPower® Technology f
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AT32UC3L0128/256 • Two Master and Two Slave Two-wire Interfaces (TWI), 400kbit/s I2C-compatible • One 8-channel Analog-to-digital Converter (ADC) with up to 12 Bits Resolution • • • • • • • – Internal Temperature Sensor Eight Analog Comparators (AC) with Optional Window Detection Capacitive Touch (CAT) Module – Hardware-assisted Atmel® AVR® QTouch® and Atmel® AVR® QMatrix Touch Acquisition – Supports QTouch and QMatrix Capture from Capacitive Touch Sensors QTouch Library Support – Capacitive Touch Butto
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AT32UC3L0128/256 1. Description The Atmel® AVR® AT32UC3L0128/256 is a complete system-on-chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and high performance.
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AT32UC3L0128/256 The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing it to a known reference clock. The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation.
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AT32UC3L0128/256 2. Overview Block Diagram aWire DATA INTERFACE M M S MEMORY PROTECTION UNIT M SAU HIGH SPEED BUS MATRIX S/M S PA PB GENERALPURPOSE I/Os HSB-PB BRIDGE B POWER MANAGER CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER 128/256 KB FLASH M REGISTERS BUS PERIPHERAL DMA CONTROLLER HSB-PB BRIDGE A CAPACITIVE TOUCH MODULE USART0 USART1 USART2 USART3 SPI TWI MASTER 0 TWI MASTER 1 DIS VDIVEN CSA[16:0] CSB[16:0] SMP SYNC RXD TXD CLK RTS, CTS SCK GCLK_IN[1..0] GCLK[4..
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AT32UC3L0128/256 2.2 Configuration Summary Table 2-1.
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AT32UC3L0128/256 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Section 3.2.1. TQFP48/QFN48 Pinout 36 35 34 33 32 31 30 29 28 27 26 25 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 Figure 3-1.
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AT32UC3L0128/256 TLLGA48 Pinout 37 36 35 34 33 32 31 30 29 28 27 26 25 PA15 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 Figure 3-2. PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 24 23 22 21 20 19 18 17 16 15 14 38 39 40 41 42 43 44 45 46 47 48 PA21 PB10 RESET_N PB04 PB05 GND VDDCORE VDDIN PB01 PA07 PA01 13 12 11 10 9 8 7 6 5 4 3 2 1 PA02 PA05 PA00 PA06 PA22 PB03 PB02 PB00 PB12 PA03 PA08 PA09 GND 3.2 Peripheral Multiplexing on I/O Lines 3.2.
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AT32UC3L0128/256 Table 3-1.
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AT32UC3L0128/256 Table 3-1.
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AT32UC3L0128/256 3.2.3 Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed function has priority in case multiple functions are enabled on the same pin. Table 3-2. 3.2.
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AT32UC3L0128/256 Table 3-4. 3.2.6 Pin AXS=1 AXS=0 EVTO_N PA04 PA04 MCKO PA06 PB01 MSEO[1] PA07 PB11 MSEO[0] PA11 PB12 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more information about this. Table 3-5. 3.2.
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AT32UC3L0128/256 3.3 Signal Descriptions The following table gives details on signal names classified by peripheral. Table 3-7.
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AT32UC3L0128/256 Table 3-7.
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AT32UC3L0128/256 Table 3-7. Signal Descriptions List Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3 CLK Clock CTS Clear To Send RTS Request To Send RXD Receive Data Input TXD Transmit Data Output Note: I/O Input Low Output Low 1. ADCIFB: AD3 does not exist. Table 3-8. Signal Description List, Continued Signal Name Function Type Active Level Comments Power VDDCORE Core Power Supply / Voltage Regulator Output Power Input/Output 1.
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AT32UC3L0128/256 3.4 3.4.1 I/O Line Considerations JTAG Pins The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI pins have pull-up resistors when JTAG is enabled. The TCK pin always has pull-up enabled during reset. The TDO pin is an output, driven at VDDIO, and has no pull-up resistor. The JTAG pins can be used as GPIO pins and multiplexed with peripherals when the JTAG is disabled. Please refer to Section 3.2.4 on page 11 for the JTAG port connections. 3.4.
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AT32UC3L0128/256 3.4.8 RC32OUT Pin 3.4.8.1 Clock output at startup After power-up, the clock generated by the 32kHz RC oscillator (RC32K) will be output on PA20, even when the device is still reset by the Power-On Reset Circuitry. This clock can be used by the system to start other devices or to clock a switching regulator to rise the power supply voltage up to an acceptable value.
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AT32UC3L0128/256 4. Mechanical Characteristics 4.1 4.1.1 Thermal Considerations Thermal Data Table 4-1 summarizes the thermal resistance data depending on the package. Table 4-1. 4.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ JA Junction-to-ambient thermal resistance Still Air TQFP48 54.4 JC Junction-to-case thermal resistance TQFP48 15.7 JA Junction-to-ambient thermal resistance QFN48 26.0 JC Junction-to-case thermal resistance QFN48 1.
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AT32UC3L0128/256 4.2 Package Drawings Figure 4-1. TQFP-48 Package Drawing Table 4-2. Device and Package Maximum Weight 140 Table 4-3. mg Package Characteristics Moisture Sensitivity Level Table 4-4.
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AT32UC3L0128/256 Figure 4-2. Note: QFN-48 Package Drawing The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 4-5. Device and Package Maximum Weight 140 Table 4-6. mg Package Characteristics Moisture Sensitivity Level Table 4-7.
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AT32UC3L0128/256 Figure 4-3. TLLGA-48 Package Drawing Table 4-8. Device and Package Maximum Weight 39.3 Table 4-9. mg Package Characteristics Moisture Sensitivity Level Table 4-10.
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AT32UC3L0128/256 4.3 Soldering Profile Table 4-11 gives the recommended soldering profile from J-STD-20. Table 4-11.
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AT32UC3L0128/256 5. Ordering Information Table 5-1.
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AT32UC3L0128/256 6. Errata 6.1 6.1.1 Rev. C SCIF 1. The RC32K output on PA20 is not always permanently disabled The RC32K output on PA20 may sometimes re-appear. Fix/Workaround Before using RC32K for other purposes, the following procedure has to be followed in order to properly disable it: - Run the CPU on RCSYS - Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT - Enable RC32K by writing a one to SCIF.RC32KCR.
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AT32UC3L0128/256 4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. 5.
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AT32UC3L0128/256 eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency. This results in premature loss of charge from the sense capacitors and thus increased variability of the acquired count values. Fix/Workaround Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11, 13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register. 2.
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AT32UC3L0128/256 - Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as zero. 2. PLLCOUNT value larger than zero can cause PLLEN glitch Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN signal during asynchronous wake up. Fix/Workaround The lock-masking mechanism for the PLL should not be used. The PLLCOUNT field of the PLL Control Register should always be written to zero. 3.
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AT32UC3L0128/256 4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. 5.
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AT32UC3L0128/256 Disable the Ready interrupt in the interrupt handler when receiving the interrupt. When an operation that triggers the Busy/Ready bit is started, wait until the ready bit is low in the Status Register before enabling the interrupt. 6.2.6 TC 1. Channel chaining skips first pulse for upper channel When chaining two channels using the Block Mode Register, the first pulse of the clock between the channels is skipped.
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AT32UC3L0128/256 Issue a dummy read to address 0x100000000 before MEMORY_SPEED_REQUEST command and use this formula instead: issuing the 7f aw f sab = ---------------CV – 3 6.2.9 Flash 1. Corrupted data in flash may happen after flash page write operations After a flash page write operation from an external in situ programmer, reading (data read or code fetch) in flash may fail. This may lead to an exception or to others errors derived from this corrupted read access.
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AT32UC3L0128/256 The flash programming time is now: Table 6-1. Flash Characteristics Symbol Parameter TFPP Page programming time TFPE Page erase time TFFP Fuse programming time TFEA Full chip erase time (EA) TFCE JTAG chip erase time (CHIP_ERASE) Conditions Min Typ Max Unit 7.5 7.5 fCLK_HSB= 50MHz 1 ms 9 fCLK_HSB= 115kHz 250 Fix/Workaround None. 4. Power Manager 5.
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AT32UC3L0128/256 Under certain circumstances, the lock signal from the Phase Locked Loop (PLL) oscillator may not go back to zero after the PLL oscillator has been disabled. This can cause the propagation of clock signals with the wrong frequency to parts of the system that use the PLL clock. Fix/Workaround PLL must be turned off before entering STOP, DEEPSTOP or STATIC sleep modes. If PLL has been turned off, a delay of 30us must be observed after the PLL has been enabled again before the SCIF.
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AT32UC3L0128/256 6.3.5 GPIO 1. Clearing Interrupt flags can mask other interrupts When clearing interrupt flags in a GPIO port, interrupts on other pins of that port, happening in the same clock cycle will not be registered. Fix/Workaround Read the PVR register of the port before and after clearing the interrupt to see if any pin change has happened while clearing the interrupt. If any change occurred in the PVR between the reads, they must be treated as an interrupt. 6.3.6 SPI 1.
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AT32UC3L0128/256 6.3.7 TWI 1. TWIS may not wake the device from sleep mode If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condition, the CPU may not wake upon a TWIS address match. The request is NACKed. Fix/Workaround When using the TWI address match to wake the device from sleep, do not switch to sleep modes deeper than Frozen.
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AT32UC3L0128/256 Fix/Workaround Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle for the upper channel. After the dummy cycle has been generated, indicated by the SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real values. 6.3.10 ADCIFB 1. ADCIFB DMA transfer does not work with divided PBA clock DMA requests from the ADCIFB will not be performed when the PBA clock is slower than the HSB clock.
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AT32UC3L0128/256 6.3.12 aWire 1. aWire MEMORY_SPEED_REQUEST command does not return correct CV The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to the formula in the aWire Debug Interface chapter. Fix/Workaround Issue a dummy read to address 0x100000000 before issuing the MEMORY_SPEED_REQUEST command and use this formula instead: 7f aw f sab = ---------------CV – 3 6.3.13 Flash 1.
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AT32UC3L0128/256 7. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 7.1 7.2 7.3 Rev. C – 06/2013 1. Updated the datasheet with new Atmel blue logo and the last page. 2. Added Flash errata. Rev. B – 01/2012 1. Description: DFLL frequency is 20 to 150MHz, not 40 to 150MHz. 2. Description: “One touch sensor can be configured to operate autonomously...
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AT32UC3L0128/256 Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 4 2.1 Block Diagram ...................................................................................................5 2.
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