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Features

• High Performance, Low Power Atmel

32-bit AVR

Microcontroller

– Compact Single-cycle RISC Instruction Set including DSP Instructions

– Read Modify Write Instructions and Atomic Bit Manipulation

– Performance

• Up to 64DMIPS Running at 50MHz from Flash (1 Flash Wait State)

• Up to 36DMIPS Running at 25MHz from Flash (0 Flash Wait State)

– Memory Protection Unit (MPU)

• Secure Access Unit (SAU) providing User Defined Peripheral Protection

• picoPower

Technology for Ultra-low Power Consumption

• Multi-hierarchy Bus System

– High-performance Data Transfers on Separate Buses for Increased Performance

– 12 Peripheral DMA Channels improve Speed for Peripheral Communication

• Internal High-speed Flash

– 64Kbytes, 32Kbytes, and 16Kbytes Versions

– Single-cycle Access up to 25MHz

–FlashVault

™

Technology Allows Pre-programmed Secure Library Support for End

User Applications

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 100,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User Defined Configuration Area

• Internal High-speed SRAM, Single-cycle Access at Full Speed

– 16Kbytes (64Kbytes and 32Kbytes Flash), or 8Kbytes (16Kbytes Flash)

• Interrupt Controller (INTC)

– Autovectored Low Latency Interrupt Service with Programmable Priority

• External Interrupt Controller (EIC)

• Peripheral Event System for Direct Peripheral to Peripheral Communication

• System Functions

– Power and Clock Manager

– SleepWalking

™

Power Saving Control

– Internal System RC Oscillator (RCSYS)

– 32KHz Oscillator

– Multipurpose Oscillator and Digital Frequency Locked Loop (DFLL)

• Windowed Watchdog Timer (WDT)

• Asynchronous Timer (AST) with Real-time Clock Capability

– Counter or Calendar Mode Supported

• Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency

• Six 16-bit Timer/Counter (TC) Channels

– External Clock Inputs, PWM, Capture and Various Counting Capabilities

• PWM Channels on All I/O Pins (PWMA)

– 8-bit PWM up to 150MHz Source Clock

• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– Independent Baudrate Generator, Support for SPI

– Support for Hardware Handshaking

• One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals

– Up to 15 SPI Slaves can be Addressed

• Two Master and Two Slave Two-wire Interface (TWI), 400kbit/s I

C-compatible

• One 8-channel Analog-to-digital Converter (ADC) with up to 12 Bits Resolution

– Internal Temperature Sensor

32099G–06/2011

32-bit AVR

Microcontroller

AT32UC3L064

AT32UC3L032

AT32UC3L016

Preliminary

Summary of content (110 pages)

PAGE 1
Features • High Performance, Low Power Atmel® 32-bit AVR® Microcontroller • • • • • • • • • • • • • • • • • – Compact Single-cycle RISC Instruction Set including DSP Instructions – Read Modify Write Instructions and Atomic Bit Manipulation – Performance • Up to 64DMIPS Running at 50MHz from Flash (1 Flash Wait State) • Up to 36DMIPS Running at 25MHz from Flash (0 Flash Wait State) – Memory Protection Unit (MPU) • Secure Access Unit (SAU) providing User Defined Peripheral Protection picoPower® Technolo
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AT32UC3L016/32/64 • Eight Analog Comparators (AC) with Optional Window Detection • Capacitive Touch (CAT) Module • • • • • – Hardware Assisted Atmel® AVR® QTouch® and Atmel® AVR® QMatrix® Touch Acquisition – Supports QTouch and QMatrix Capture from Capacitive Touch Sensors QTouch Library Support – Capacitive Touch Buttons, Sliders, and Wheels – QTouch and QMatrix Acquisition On-chip Non-intrusive Debug System – Nexus Class 2+, Runtime Control, Non-intrusive Data and Program Trace – aWire™ Single-pin Pro
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AT32UC3L016/32/64 1. Description The Atmel ® AVR ® AT32UC3L is a complete System-on-chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and high performance.
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AT32UC3L016/32/64 The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. The Pulse Width Modulation controller (PWMA) provides 8-bit PWM channels which can be synchronized and controlled from a common timer.
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AT32UC3L016/32/64 2.
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AT32UC3L016/32/64 2.2 Configuration Summary Table 2-1.
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AT32UC3L016/32/64 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Section 3.2. TQFP48/QFN48 Pinout 36 35 34 33 32 31 30 29 28 27 26 25 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 Figure 3-1.
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AT32UC3L016/32/64 TLLGA48 Pinout 37 36 35 34 33 32 31 30 29 28 27 26 25 PA15 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 Figure 3-2.
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AT32UC3L016/32/64 3.2 Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed signals Each GPIO line can be assigned to one of the peripheral functions.The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1.
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AT32UC3L016/32/64 Table 3-1.
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AT32UC3L016/32/64 Refer to the ”TWI Pin Characteristics(1)” on page 49 for a description of the electrical properties of the TWI, 5V Tolerant, and SMBUS pins. 3.2.2 Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed function has priority in case multiple functions are enabled on the same pin. Table 3-2. 3.2.
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AT32UC3L016/32/64 Table 3-4. 3.2.5 Pin AXS=1 AXS=0 MDO[2] PA16 PB03 MDO[1] PA15 PB02 MDO[0] PA14 PB09 EVTO_N PA04 PA04 MCKO PA06 PB01 MSEO[1] PA07 PB11 MSEO[0] PA11 PB12 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more information about this. Table 3-5. 3.2.
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AT32UC3L016/32/64 3.3 Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-7.
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AT32UC3L016/32/64 Table 3-7.
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AT32UC3L016/32/64 Table 3-7. Signal Descriptions List Universal Synchronous/Asynchronous Receiver/Transmitter - USART0, USART1, USART2, USART3 CLK Clock CTS Clear To Send RTS Request To Send RXD Receive Data Input TXD Transmit Data Output Note: I/O Input Low Output Low 1. ADCIFB: AD3 does not exist. Table 3-8. Signal Description List, Continued Signal Name Function Type Active Level Comments Power VDDCORE Core Power Supply / Voltage Regulator Output Power Input/Output 1.
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AT32UC3L016/32/64 3.4 3.4.1 I/O Line Considerations JTAG Pins The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI pins have pull-up resistors when JTAG is enabled. The TCK pin always has pull-up enabled during reset. The TDO pin is an output, driven at VDDIO, and has no pull-up resistor. The JTAG pins can be used as GPIO pins and multiplexed with peripherals when the JTAG is disabled. Please refer to Section 3.2.3 on page 11 for the JTAG port connections. 3.4.
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AT32UC3L016/32/64 3.4.8 RC32OUT Pin 3.4.8.1 Clock output at startup After power-up, the clock generated by the 32kHz RC oscillator (RC32K) will be output on PA20, even when the device is still reset by the Power-On Reset Circuitry. This clock can be used by the system to start other devices or to clock a switching regulator to rise the power supply voltage up to an acceptable value.
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AT32UC3L016/32/64 4. Processor and Architecture Rev: 2.1.0.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 4.
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AT32UC3L016/32/64 single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 4.
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AT32UC3L016/32/64 OCD interface Reset interface Overview of the AVR32UC CPU Interrupt controller interface Figure 4-1. OCD system Power/ Reset control AVR32UC CPU pipeline MPU 4.3.
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AT32UC3L016/32/64 Figure 4-2. The AVR32UC Pipeline MUL IF ID Prefetch unit Decode unit Regfile Read ALU LS 4.3.2 Multiply unit Regfile write ALU unit Load-store unit AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts.
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AT32UC3L016/32/64 address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. 4.3.2.5 Instructions with Unaligned Reference Support Instruction Supported Alignment ld.d Word st.
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AT32UC3L016/32/64 4.4 4.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 4-3.
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AT32UC3L016/32/64 Figure 4-5. The Status Register Low Halfword Bit 15 Bit 0 - T - - - - - - - - L Q V N Z C Bit name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 4.4.3 Processor States 4.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2. Table 4-2. Overview of Execution Modes, their Priorities and Privilege Levels.
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AT32UC3L016/32/64 Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 4.4.4 Secure State The AVR32 can be set in a secure state, that allows a part of the code to execute in a state with higher security levels. The rest of the code can not access resources reserved for this secure code. Secure State is used to implement FlashVault technology. Refer to the AVR32UC Technical Reference Manual for details.
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AT32UC3L016/32/64 Table 4-3.
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AT32UC3L016/32/64 Table 4-3. 4.
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AT32UC3L016/32/64 relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up appropriately. The same mechanisms are used to service all different types of events, including interrupt requests, yielding a uniform event handling scheme.
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AT32UC3L016/32/64 4.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from timecritical event handlers.
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AT32UC3L016/32/64 than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 4-4 on page 31. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floatingpoint unit.
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AT32UC3L016/32/64 Table 4-4.
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AT32UC3L016/32/64 5. Memories 5.
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AT32UC3L016/32/64 5.3 Peripheral Address Map Table 5-3.
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AT32UC3L016/32/64 Table 5-3.
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AT32UC3L016/32/64 The following GPIO registers are mapped on the local bus: Table 5-4.
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AT32UC3L016/32/64 6. Supply and Startup Considerations 6.1 6.1.1 Supply Considerations Power Supplies The AT32UC3L has several types of power supply pins: •VDDIO: Powers I/O lines. Voltage is 1.8 to 3.3V nominal. •VDDIN: Powers I/O lines and the internal regulator. Voltage is 1.8 to 3.3V nominal. •VDDANA: Powers the ADC. Voltage is 1.8V nominal. •VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal. The ground pins GND are common to VDDCORE, VDDIO, and VDDIN.
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AT32UC3L016/32/64 6.1.3.1 3.3V Single Supply Mode In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin) and its output feeds VDDCORE. Figure 6-2 shows the power schematics to be used for 3.3V single supply mode. All I/O lines will be powered by the same power (VDDIN=VDDIO). Figure 6-2. 3.3V Single Supply Mode + 1.98-3.
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AT32UC3L016/32/64 6.1.3.2 1.8V Single Supply Mode In 1.8V single supply mode the internal regulator is not used, and VDDIO and VDDCORE are powered by a single 1.8V supply as shown in Figure 6-3. All I/O lines will be powered by the same power (VDDIN = VDDIO = VDDCORE). Figure 6-3. 1.8V Single Supply Mode. + 1.62-1.
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AT32UC3L016/32/64 6.1.3.3 3.3V Supply Mode with 1.8V Regulated I/O Lines In this mode, the internal regulator is connected to the 3.3V source and its output is connected to both VDDCORE and VDDIO as shown in Figure 6-4. This configuration is required in order to use Shutdown mode. Figure 6-4. 3.3V Supply Mode with 1.8V Regulated I/O Lines 1.98-3.
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AT32UC3L016/32/64 6.1.4 Power-up Sequence 6.1.4.1 Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Table 7-3 on page 42. Recommended order for power supplies is also described in this chapter. 6.1.4.2 Minimum Rise Rate The integrated Power-on Reset (POR33) circuitry monitoring the VDDIN powering supply requires a minimum rise rate for the VDDIN power supply. See Table 7-3 on page 42 for the minimum rise rate value.
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AT32UC3L016/32/64 7. Electrical Characteristics 7.1 Disclaimer All values in this chapter are preliminary and subject to change without further notice. 7.2 Absolute Maximum Ratings* Table 7-1. Absolute Maximum Ratings Operating temperature..................................... -40°C to +85°C *NOTICE: Storage temperature...................................... -60°C to +150°C Voltage on input pins (except for 5V pins) with respect to ground ...............................................................
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AT32UC3L016/32/64 Table 7-3. Supply Rise Rates and Order(1) Rise Rate Symbol Parameter Min Max Unit VVDDIO DC supply peripheral I/Os 0 2.5 V/µs VVDDIN DC supply peripheral I/Os and internal regulator 0.002 2.5 V/µs Slower rise time requires external power-on reset circuit. VVDDCORE DC supply core 0 2.5 V/µs Rise before or at the same time as VDDIO VVDDANA Analog supply voltage 0 2.5 V/µs Rise together with VDDCORE Note: 7.4 Comment 1.
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AT32UC3L016/32/64 – Corresponds to the 3.3V supply mode with 1.8V regulated I/O lines, please refer to the Supply and Startup Considerations section for more details • Equivalent to the 3.3V single supply mode • Consumption in 1.8V single supply mode can be estimated by subtracting the regulator static current • Operating conditions external core supply (Figure 7-2) - used only when noted – VVDDIN = VVDDCORE = 1.8V – Corresponds to the 1.
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AT32UC3L016/32/64 Table 7-5. Mode Power Consumption for Different Operating Modes Conditions Active(1) Measured on Consumption Typ -CPU running a recursive Fibonacci algorithm 260 -CPU running a division algorithm 165 Idle(1) 92 (1) (1) 47 Stop 37 DeepStop 23 -OSC32K and AST stopped -Internal core supply Static Shutdown Amp0 10 µA -OSC32K running -AST running at 1KHz -External core supply (Figure 7-2) 5.3 -OSC32K and AST stopped -External core supply (Figure 7-2) 4.
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AT32UC3L016/32/64 Figure 7-2. Measurement Schematic, External Core Supply Amp0 VDDIN VDDIO VDDCORE VDDANA 7.5.1 Peripheral Power Consumption The values in Table 7-6 are measured values of power consumption under the following conditions. • Operating conditions internal core supply (Figure 7-1) – VVDDIN = 3.0V – VVDDCORE = 1.62V, supplied by the internal regulator – Corresponds to the 3.3V supply mode with 1.
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AT32UC3L016/32/64 . Table 7-6. Peripheral Typical Current Consumption by Peripheral(2) Typ Consumption Active ACIFB 14.0 ADCIFB(1) 14.9 AST 5.6 AW USART 6.8 CAT 12.4 EIC 1.3 FREQM 3.2 GLOC 0.4 GPIO 15.9 PWMA 2.5 SPI 7.6 TC 7.2 TWIM 5.1 TWIS 3.2 USART 12.3 WDT 2.3 Unit µA/MHz Notes: 1. Includes the current consumption on VDDANA and ADVREFP. 2. These numbers are valid for the measured condition only and must not be extrapolated to other frequencies.
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AT32UC3L016/32/64 7.6 I/O Pin Characteristics Table 7-7. Normal I/O Pin Characteristics(1) Symbol Parameter RPULLUP Pull-up resistance VIL Input low-level voltage VIH Input high-level voltage VOL Output low-level voltage VOH Output high-level voltage fMAX Output frequency(2) tRISE Rise time(2) Condition Min Typ Max Units 75 100 145 kOhm VVDD = 3.0V -0.3 0.3*VVDD VVDD = 1.62V -0.3 0.3*VVDD VVDD = 3.6V 0.7*VVDD VVDD + 0.3 VVDD = 1.98V 0.7*VVDD VVDD + 0.3 VVDD = 3.
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AT32UC3L016/32/64 Table 7-8. High-drive I/O Pin Characteristics(1) Symbol Parameter Condition Min Typ Max VIH Input high-level voltage VOL Output low-level voltage VOH Output high-level voltage Output frequency, all Highdrive I/O pins, except PA08 and PA09(2) VVDD = 3.0V, load = 10pF 45 fMAX VVDD = 3.0V, load = 30pF 23 Rise time, all High-drive I/O pins, except PA08 and PA09(2) VVDD = 3.0V, load = 10pF 4.7 tRISE VVDD = 3.0V, load = 30pF 11.5 VVDD = 3.0V, load = 10pF 4.
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AT32UC3L016/32/64 Table 7-9. High-drive I/O, 5V Tolerant, Pin Characteristics(1) Symbol Parameter VOH Output high-level voltage fMAX Output frequency(2) tRISE Rise time(2) (2) tFALL Fall time ILEAK Input leakage current CIN Input capacitance Notes: Condition Min Typ VVDD = 3.0V, IOH = 6mA VVDD-0.4 VVDD = 1.62V, IOH = 4mA VVDD-0.4 Max Units V VVDD = 3.0V, load = 10pF 87 VVDD = 3.0V, load = 30pF 58 VVDD = 3.0V, load = 10pF 2.3 VVDD = 3.0V, load = 30pF 4.3 VVDD = 3.
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AT32UC3L016/32/64 7.7 Oscillator Characteristics 7.7.1 Oscillator 0 (OSC0) Characteristics 7.7.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN. Table 7-11. Digital Clock Characteristics Symbol Parameter fCPXIN XIN clock frequency tCPXIN XIN clock duty cycle tSTARTUP Startup time CIN XIN input capacitance 7.7.1.2 Conditions Min Typ Max 40 Units 50 MHz 60 % 0 TQFP48 package 7.
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AT32UC3L016/32/64 Figure 7-3. Oscillator Connection CLEXT XOUT UC3L Ci CL XIN CLEXT 7.7.2 32KHz Crystal Oscillator (OSC32K) Characteristics Figure 7-3 and the equation above also applies to the 32 KHz oscillator connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can then be found in the crystal datasheet. Table 7-13.
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AT32UC3L016/32/64 7.7.3 Digital Frequency Locked Loop (DFLL) Characteristics Table 7-14. Symbol Digital Frequency Locked Loop Characteristics Parameter Conditions (2) fOUT Output frequency fREF Reference frequency(2) FINE resolution FINE > 100, all COARSE values Frequency drift over voltage and temperature Accuracy(2) IDFLL Power consumption tSTARTUP Startup time(2) tLOCK Lock time Notes: Min Typ Max Unit 40 150 MHz 8 150 kHz 0.
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AT32UC3L016/32/64 Figure 7-4. DFLL Open Loop Frequency Variation(1) DFLL Open Loop Frequency variation 160 150 Frequencies (MHz) 140 130 1,98V 120 1,8V 1.62V 110 100 90 80 -40 -20 0 20 40 60 80 Tem pera ture Note: 1. The plot shows a typical behaviour for coarse = 99 and fine = 255 in open loop mode. 7.7.4 120MHz RC Oscillator (RC120M) Characteristics Table 7-15.
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AT32UC3L016/32/64 7.7.5 32kHz RC Oscillator (RC32K) Characteristics Table 7-16. Symbol 32kHz RC Oscillator Characteristics Parameter Conditions (1) Min Typ Max Unit 20 32 44 kHz fOUT Output frequency IRC32K Current consumption 0.6 µA tSTARTUP Startup time 100 µs Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. 7.7.
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AT32UC3L016/32/64 Table 7-20. Flash Endurance and Data Retention Symbol Parameter NFARRAY Array endurance (write/page) 100k NFFUSE General Purpose fuses endurance (write/bit) 10k tRET Data retention 15 7.9 Min Typ Max Unit cycles years Analog Characteristics 7.9.1 Voltage Regulator Characteristics Table 7-21. VREG Electrical Characteristics Symbol Parameter VVDDIN Input voltage range VVDDCORE Output voltage, calibrated value Condition Min Typ Max 1.98 3.3 3.
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AT32UC3L016/32/64 7.9.2 Power-on Reset 18 Characteristics Table 7-23. POR18 Characteristics Symbol Parameter Condition VPOT+ Voltage threshold on VVDDCORE rising VPOT- Voltage threshold on VVDDCORE falling tDET Detection time Typ Max 1.45 1.58 Units V 1.2 Time with VDDCORE < VPOTnecessary to generate a reset signal 1.32 460 µs POR18 Operating Principles VVDDCORE Figure 7-5.
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AT32UC3L016/32/64 7.9.3 Power-on Reset 33 Characteristics Table 7-24. POR33 Characteristics Symbol Parameter Condition VPOT+ Voltage threshold on VVDDIN rising VPOT- Voltage threshold on VVDDIN falling tDET Detection time Time with VDDIN < VPOTnecessary to generate a reset signal 460 µs IPOR33 Current consumption After tRESET 15 µA tSTARTUP Startup time 400 µs Typ Max 1.49 1.58 Units V 1.3 1.45 POR33 Operating Principles VVDDIN Figure 7-6. Min Reset VPOT+ VPOT- 7.9.
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AT32UC3L016/32/64 Table 7-26. BOD Characteristics Symbol Parameter Condition VHYST BOD hysteresis T = 25°C 10 mV tDET Detection time Time with VDDCORE < BODLEVEL necessary to generate a reset signal 1 µs IBOD Current consumption 16 µA tSTARTUP Startup time 5 µs 7.9.5 Min Typ Max Units Supply Monitor 33 Characteristics Table 7-27. Symbol VTH SM33 Characteristics Parameter Voltage threshold Condition (1) Calibrated , T = 25°C Min Typ Max Units 1.675 1.75 1.
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AT32UC3L016/32/64 7.9.6 Analog to Digital Converter Characteristics Table 7-28. ADC Characteristics Symbol Parameter Conditions fADC ADC clock frequency tSTARTUP Startup time Return from Idle Mode tCONV Conversion time (latency) fADC = 6MHz Throughput rate Min Typ 10-bit resolution mode 6 8-bit resolution mode 6 15 11 VVDD > 3.0V, fADC = 6MHz, 10-bit resolution mode, low impedance source 460 VVDD > 3.
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AT32UC3L016/32/64 Figure 7-7. ADC Input RSOURCE Positive Input RONCHIP CSOURCE VIN CONCHIP ADCVREFP/2 The minimum sample and hold time (in ns) can be found using this formula: t SAMPLEHOLD ≥ ( R ONCHIP + R OFFCHIP ) × ( C ONCHIP + C OFFCHIP ) × ln ( 2 n+1 ) Where n is the number of bits in the conversion. t SAMPLEHOLD is defined by the SHTIM field in the ADCIFB ACR register. Please refer to the ADCIFB chapter for more information. 7.9.6.2 Table 7-30.
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AT32UC3L016/32/64 7.9.7 Temperature Sensor Characteristics Temperature Sensor Characteristics(1) Table 7-32. Symbol Parameter Condition Min Typ Max Units Gradient 1 mV/°C ITS Current consumption 0.5 µA tSTARTUP Startup time 0 µs Note: 1. The Temperature Sensor is not calibrated. The accuracy of the Temperature Sensor is governed by the ADC accuracy. 7.9.8 Analog Comparator Characteristics Table 7-33.
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AT32UC3L016/32/64 7.9.9 Capacitive Touch Characteristics 7.9.9.1 Table 7-34. Discharge Current Source DICS Characteristics Symbol Parameter RREF Internal resistor 120 kOhm k Trim step size 0.7 % 7.9.9.2 Table 7-35.
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AT32UC3L016/32/64 7.10 Timing Characteristics 7.10.1 Startup, Reset, and Wake-up Timing The startup, reset, and wake-up timings are calculated using the following formula: t = t CONST + N CPU × t CPU Where t CONST and N CPU are found in Table 7-36. t CPU is the period of the CPU clock. If another clock source than RCSYS is selected as CPU clock the startup time of the oscillator, t OSCSTART , must added to the wake-up time in the stop, deepstop, and static sleep modes.
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AT32UC3L016/32/64 7.10.3 USART in SPI Mode Timing 7.10.3.1 Master mode Figure 7-8. USART in SPI Master Mode With (CPOL= CPHA= 0) or (CPOL= CPHA= 1) SPCK MISO USPI0 USPI1 MOSI USPI2 Figure 7-9. USART in SPI Master Mode With (CPOL= 0 and CPHA= 1) or (CPOL= 1 and CPHA= 0) SPCK MISO USPI3 USPI4 MOSI USPI5 Table 7-38.
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AT32UC3L016/32/64 Maximum SPI Frequency, Master Output The maximum SPI master output frequency is given by the following formula: 1 f CLKSPI × 2 f SPCKMAX = MIN (f PINMAX,------------, -----------------------------) SPIn 9 Where SPIn is the MOSI delay, USPI2 or USPI5 depending on CPOL and NCPHA. f PINMAX is the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the maximum frequency of the pins. f CLKSPI is the maximum frequency of the CLK_SPI.
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AT32UC3L016/32/64 Figure 7-12. USART in SPI Slave Mode NPCS Timing USPI12 USPI13 USPI14 USPI15 SPCK, CPOL=0 SPCK, CPOL=1 NSS Table 7-39.
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AT32UC3L016/32/64 The maximum SPI slave output frequency is given by the following formula: f CLKSPI × 2 1 f SPCKMAX = MIN (-----------------------------, f PINMAX,------------------------------------) 9 SPIn + t SETUP Where SPIn is the MISO delay, USPI6 or USPI9 depending on CPOL and NCPHA. T SETUP is the SPI master setup time. Please refer to the SPI master datasheet for T SETUP . f CLKSPI is the maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this clock.
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AT32UC3L016/32/64 Table 7-40. SPI Timing, Master Mode(1) Symbol Parameter SPI0 MISO setup time before SPCK rises SPI1 MISO hold time after SPCK rises SPI2 SPCK rising to MOSI delay SPI3 MISO setup time before SPCK falls SPI4 MISO hold time after SPCK falls SPI5 SPCK falling to MOSI delay Note: Conditions Min Max Units 28.4 + (tCLK_SPI)/2 VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF 0 7.1 ns 22.8 + (tCLK_SPI)/2 0 11.0 1.
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AT32UC3L016/32/64 Figure 7-16. SPI Slave Mode With (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1) SPCK MISO SPI9 MOSI SPI10 Figure 7-17. SPI11 SPI Slave Mode NPCS Timing SPI12 SPI13 SPI14 SPI15 SPCK, CPOL=0 SPCK, CPOL=1 NPCS Table 7-41. SPI Timing, Slave Mode(1) Symbol Parameter SPI6 SPCK falling to MISO delay SPI7 MOSI setup time before SPCK rises 49.4 SPI8 MOSI hold time after SPCK rises 4.
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AT32UC3L016/32/64 The maximum SPI slave input frequency is given by the following formula: 1 f SPCKMAX = MIN (f CLKSPI,------------) SPIn Where SPIn is the MOSI setup and hold time, SPI7 + SPI8 or SPI10 + SPI11 depending on CPOL and NCPHA. f CLKSPI is the maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this clock.
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AT32UC3L016/32/64 Table 7-42. TWI-Bus Timing Requirements Minimum Symbol Parameter tSU-DAT-TWI Data set-up time tSU-DAT tLOW-TWI Mode Requirement Standard 250 Fast 100 - Device - Standard 4.7 Fast 1.3 TWCK LOW period tLOW - tHIGH TWCK HIGH period fTWCK TWCK frequency - Standard 4.0 Fast 0.6 Standard Notes: Maximum Requirement Unit 2tclkpb - ns tclkpb - - 4tclkpb - μs tclkpb - - 8tclkpb - μs 100 - Fast Device 400 1 -----------------------12t clkpb kHz 1.
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AT32UC3L016/32/64 7.10.6 JTAG Timing Figure 7-18. JTAG Interface Signals JTAG2 TCK JTAG0 JTAG1 TMS/TDI JTAG3 JTAG4 JTAG7 JTAG8 TDO JTAG5 JTAG6 Boundary Scan Inputs Boundary Scan Outputs JTAG9 JTAG10 Table 7-43. JTAG Timings(1) Symbol Parameter JTAG0 TCK Low Half-period 23.2 JTAG1 TCK High Half-period 8.8 JTAG2 TCK Period 32.
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AT32UC3L016/32/64 8. Mechanical Characteristics 8.1 8.1.1 Thermal Considerations Thermal Data Table 8-1 summarizes the thermal resistance data depending on the package. Table 8-1. 8.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ θJA Junction-to-ambient thermal resistance Still Air TQFP48 63.2 θJC Junction-to-case thermal resistance TQFP48 21.8 θJA Junction-to-ambient thermal resistance QFN48 28.3 θJC Junction-to-case thermal resistance QFN48 2.
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AT32UC3L016/32/64 8.2 Package Drawings Figure 8-1. TQFP-48 Package Drawing Table 8-2. Device and Package Maximum Weight 140 Table 8-3. mg Package Characteristics Moisture Sensitivity Level Table 8-4.
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AT32UC3L016/32/64 Figure 8-2. Note: QFN-48 Package Drawing The exposed pad is not connected to anything. Table 8-5. Device and Package Maximum Weight 140 Table 8-6. mg Package Characteristics Moisture Sensitivity Level Table 8-7.
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AT32UC3L016/32/64 Figure 8-3. TLLGA-48 Package Drawing Table 8-8. Device and Package Maximum Weight 39.3 Table 8-9. mg Package Characteristics Moisture Sensitivity Level Table 8-10.
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AT32UC3L016/32/64 8.3 Soldering Profile Table 8-11 gives the recommended soldering profile from J-STD-20. Table 8-11.
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AT32UC3L016/32/64 9. Ordering Information Table 9-1.
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AT32UC3L016/32/64 10. Errata 10.1 10.1.1 Rev. E Processor and Architecture Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions. Privilege violation when using interrupts in application mode with protected system stack If the system stack is protected by the MPU and an interrupt occurs in application mode, an MPU DTLB exception will occur.
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AT32UC3L016/32/64 If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walking, all PB clocks will be masked except the PB clock to the sleepwalking module. Fix/Workaround Mask all clock requests in the PM.PPCR register before going into idle or frozen mode. 10.1.4 SCIF The FLO lock bit (FLOCR.LOCK) does not work The FLO lock bit does not work and will always read as zero. Fix/Workaround Wait for 32 reference clock cycles after the tuner is enabled, then read the FLO.
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AT32UC3L016/32/64 10.1.6 WDT Clearing the Watchdog Timer (WDT) counter in second half of timeout period will issue a Watchdog reset If the WDT counter is cleared in the second half of the timeout period, the WDT will immediately issue a Watchdog reset. Fix/Workaround Use twice as long timeout period as needed and clear the WDT counter within the first half of the timeout period. If the WDT counter is cleared after the first half of the timeout period, you will get a Watchdog reset immediately.
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AT32UC3L016/32/64 properly. Fix/Workaround Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS. SPI RDR.PCS is not correct The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not correctly indicate the value on the NPCS pins at the end of a transfer. Fix/Workaround Do not use the PCS field of the SPI RDR. 10.1.9 TWI TWIM SR.
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AT32UC3L016/32/64 Ensure that duty cycle writes from the user interface are not performed in a PWMA period when an incoming peripheral event is expected. 10.1.10 ADCIFB Using STARTUPTIME larger than 0x1F will freeze the ADC Writing a value larger than 0x1F to the Startup Time field in the ADC Configuration Register (ACR.STARTUP) will freeze the ADC, and the Busy Status bit in the Status Register (SR.BUSY) will never be cleared. Fix/Workaround Do not write values larger than 0x1F to ACR.STARTUP. 10.1.
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AT32UC3L016/32/64 Solution 1: Disable OSC0 by writing a zero to the Oscillator Enable bit in the System Control Interface (SCIF) Oscillator Control Register (SCIF.OSC0CTRL.OSCEN) before going to a sleep mode where OSC0 is disabled. Solution 2: Pull down or up XIN0 or XOUT0 with 1MOhm resistor. 10.1.14 I/O Pins PA17 has low ESD tolerance PA17 only tolerates 500V ESD pulses (Human Body Model). Fix/Workaround Care must be taken during manufacturing and PCB design. 10.2 10.2.1 Rev.
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AT32UC3L016/32/64 Before going to sleep modes where RCSYS is stopped, make sure the division factor between CPU/HSB and PBx frequencies is less than or equal to 4. External reset in Shutdown mode If an external reset is asserted while the device is in Shutdown mode, the Power Manager will register this as a Power-on reset (POR), and not as a SLEEP reset, in the Reset Cause register (RCAUSE) Fix/Workaround None.
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AT32UC3L016/32/64 Wait for 32 reference clock cycles after the tuner is enabled, then read the FLO.NOLOCK bit to check if it is set. If it is set, a lock can not be obtained for this configuration of reference clock and target ratio. PCLKSR.OSC32RDY bit might not be cleared after disabling OSC32K In some cases the OSC32RDY bit in the PCLKSR register will not be cleared when OSC32K is disabled. Fix/Workaround When re-enabling the OSC32K, read the PCLKSR.OSC32RDY bit.
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AT32UC3L016/32/64 10.2.7 GPIO Clearing GPIO interrupt may fail Writing a one to the GPIO.IFRC register to clear an interrupt will be ignored if interrupt is enabled for the corresponding port. Fix/Workaround Disable the interrupt, clear it by writing a one to GPIO.IFRC, then enable the interrupt. 10.2.8 SPI SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer.
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AT32UC3L016/32/64 10.2.9 TWI TWIM SR.IDLE goes high immediately when NAK is received When a NAK is received and there is a non-zero number of bytes to be transmitted, SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This does not cause any problem just by itself, but can cause a problem if software waits for SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
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AT32UC3L016/32/64 10.2.11 CAT CAT asynchronous wake will be delayed by one AST event period If the CAT detects a condition the should asynchronously wake the device in static mode, the asynchronous wake will not occur until the next AST event. For example, if the AST is generating events to the CAT every 50ms, and the CAT detects a touch at t=9200ms, the asynchronous wake will occur at t=9250ms. Fix/Workaround None.
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AT32UC3L016/32/64 Solution 1: Disable OSC0 by writing a zero to the Oscillator Enable bit in the System Control Interface (SCIF) Oscillator Control Register (SCIF.OSC0CTRL.OSCEN) before going to a sleep mode where OSC0 is disabled. Solution 2: Pull down or up XIN0 or XOUT0 with 1MOhm resistor. 10.2.14 I/O Pins PA17 has low ESD tolerance PA17 only tolerates 500V ESD pulses (Human Body Model). Fix/Workaround Care must be taken during manufacturing and PCB design. 10.3 Rev. C Not sampled. 10.4 10.4.1 Rev.
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AT32UC3L016/32/64 Transfer error will stall a transmit peripheral handshake interface If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral handshake of the active channel will stall and the PDCA will not do any more transfers on the affected peripheral handshake interface. Fix/Workaround Disable and then enable the peripheral after the transfer error. VERSION register reads 0x120 The VERSION register reads 0x120 instead of 0x122. Fix/Workaround None. 10.4.
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AT32UC3L016/32/64 Fix/Workaround None. Open Mode is not functional The Open Mode is not functional. Fix/Workaround None. VERSION register reads 0x100 The VERSION register reads 0x100 instead of 0x110. Fix/Workaround None. 10.4.5 HMATRIX In the PRAS and PRBS registers, the MxPR fields are only two bits In the PRAS and PRBS registers, the MxPR fields are only two bits wide, instead of four bits. The unused bits are undefined when reading the registers.
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AT32UC3L016/32/64 None. Clock sources will not be stopped in Static mode if the difference between CPU and PBx division factor is larger than 4 If the division factor between the CPU/HSB and PBx frequencies is more than 4 when entering a sleep mode where the system RC oscillator (RCSYS) is turned off, the high speed clock sources will not be turned off. This will result in a significantly higher power consumption during the sleep mode.
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AT32UC3L016/32/64 Writing to ICR masks any new SCIF interrupt received in the same clock cycle, regardless of write value. Fix/Workaround For every interrupt except BODDET, SM33DET, and VREGOK the PCLKSR register can be read to detect new interrupts. BODDET, SM33DET and VREGOK interrupts will not be generated if they occur whilst writing to the ICR register.
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AT32UC3L016/32/64 The DFLLIF dithering does not work. Fix/Workaround None. DFLLIF might lose fine lock when dithering is disabled When dithering is disabled and fine lock has been acquired, the DFLL might lose the fine lock resulting in up to 20% over-/undershoot. Fix/Workaround Solution 1: When the DFLL is used as main clock source, the target frequency of the DFLL should be 20% below the maximum operating frequency of the CPU. Don’t use the DFLL as clock source for frequency sensitive applications.
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AT32UC3L016/32/64 OSC32VERSION register reads 0x100 instead of 0x101. Fix/Workaround None. VREGVERSION register reads 0x100 VREGVERSION register reads 0x100 instead of 0x101. Fix/Workaround None. RC120MVERSION register reads 0x100 RC120MVERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 10.4.
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AT32UC3L016/32/64 Fix/Workaround None. GCLK5 can not be used as source for the CLK_MSR The frequency for GCLK5 can not be measured by the FREQM. Fix/Workaround None. 10.4.11 GPIO GPIO interrupt can not be cleared when interrupts are disabled The GPIO interrupt can not be cleared unless the interrupt is enabled for the pin. Fix/Workaround Enable interrupt for the corresponding pin, then clear the interrupt. VERSION register reads 0x210 The VERSION register reads 0x210 instead of 0x211. Fix/Workaround None.
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AT32UC3L016/32/64 Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK.
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AT32UC3L016/32/64 Enable the TWIM first and then enable the TWD and TWCK peripheral pins in the GPIO controller. If it is necessary to disable the TWIM, first disable the TWD and TWCK peripheral pins in the GPIO controller and then disable the TWIM. TWIM SR.IDLE goes high immediately when NAK is received When a NAK is received and there is a non-zero number of bytes to be transmitted, SR.IDLE goes high immediately and does not wait for the STOP condition to be sent.
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AT32UC3L016/32/64 The duty cycle registers will be corrupted if written when the timebase counter overflows. If the duty cycle registers are written exactly when the timebase counter overflows at TOP, the duty cycle registers may become corrupted. Fix/Workaround Write to the duty cycle registers only directly after the Timebase Overflow bit in the status register is set. Open Drain mode does not work The open drain mode does not work. Fix/Workaround None.
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AT32UC3L016/32/64 Writing a value larger than 0x1F to the Startup Time field in the ADC Configuration Register (ACR.STARTUP) will freeze the ADC, and the Busy Status bit in the Status Register (SR.BUSY) will never be cleared. Fix/Workaround Do not write values larger than 0x1F to ACR.STARTUP. ADC channels six to eight are non-functional ADC channels six to eight are non-functional. Fix/Workaround None. VERSION register reads 0x100 The VERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 10.4.
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AT32UC3L016/32/64 DISHIFT field is stuck at zero The DISHIFT field in the MGCFG1, TGACFG1, TGBCFG1, and ATCFG1 registers is stuck at zero and cannot be written to a different value. Capacitor discharge time will only be determined by the DILEN field. Fix/Workaround None. MGCFG2.CONSEN field is stuck at zero The CONSEN field in the MGCFG2 register is stuck at zero and cannot be written to a different value.
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AT32UC3L016/32/64 aWire enable does not work in Static mode. Fix/Workaround None. aWire CPU clock speed robustness The aWire memory speed request command counter warps at clock speeds below approximately 5kHz. Fix/Workaround None. The aWire debug interface is reset after leaving Shutdown mode If the aWire debug mode is used as debug interface and the program enters Shutdown mode, the aWire interface will be reset when the part receives a wakeup either from the WAKE_N pin or the AST. Fix/Workaround None.
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AT32UC3L016/32/64 Fix/Workaround Solution 1: Disable OSC0 by writing a zero to the Oscillator Enable bit in the System Control Interface (SCIF) Oscillator Control Register (SCIF.OSC0CTRL.OSCEN) before going to a sleep mode where OSC0 is disabled. Solution 2: Pull down or up XIN0 and XOUT0 with 1MOhm resistor. 10.4.23 I/O Pins PB10 is not 3.3V tolerant. PB10 should be grounded on the PCB and left unused. Fix/Workaround None.
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AT32UC3L016/32/64 11. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 11.2 11.3 Rev. G - 06/2011 1. FLASHCDW: FSR register is a Read-only register. Added info about QPRUP 2. PM: Clarified POR33 masking requirements before shutdown. Added more info about wakeup sources. Added AWEN description. PPCR register reset value corrected. 3. SAU: SR.
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AT32UC3L016/32/64 11.4 13. TC: Added features and version register. 14. SAU: Added OPEN bit to config register. Added description of unlock fields. 15. TWIS: SCR is Write-only. Improved explanation of slave transmitter mode. Updated data transfer diagrams. 16. Electrical Characteristics: Added more values. Added notes on simulated and characterized values. Added pin capacitance, rise, and fall times. Added timing characteristics. Removed all TBDs. Added ADC analog input characteristics.
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AT32UC3L016/32/64 11.7 13. SCIF: Temperature sensor is connected to ADC channel 9, not 7. 14. SCIF: Updated the oscillator connection figure for OSC0 15. GPIO: Removed unimplemented features (pull-down, buskeeper, drive strength, slew rate, Schmidt trigger, open drain). 16. SPI: RDR.PCS field removed (RDR[19:16]). 17. TWIS: Figures updated. 18. ADCIFB: The sample and hold time and the startup time formulas have been corrected (ADC Configuration Register). 19. ADCIFB: Updated ADC signal names.
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AT32UC3L016/32/64 Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 4 5 6 7 2.1 Block Diagram ...................................................................................................
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AT32UC3L016/32/64 8 9 7.8 Flash Characteristics .......................................................................................54 7.9 Analog Characteristics .....................................................................................55 7.10 Timing Characteristics .....................................................................................63 Mechanical Characteristics ................................................................... 73 8.1 Thermal Considerations ........
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Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg.