Datasheet

40
32117DS–AVR-01/12
AT32UC3C
5.2 Physical Memory Map
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot. Note that AVR32UC CPU uses unsegmented
translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space
is mapped as follows:
Table 5-1. AT32UC3C Physical Memory Map
Device
Start Address
AT32UC3 Derivatives
C0512C
C1512C
C2512C
C0256C
C1256C
C2256C
C0128C
C1128C
C2128C
C064C
C164C
C264C
Embedded
SRAM
0x0000_0000 64 KB 64 KB 64 KB 64 KB 32 KB 32 KB 16 KB 16 KB
Embedded
Flash
0x8000_0000 512 KB 512 KB 256 KB 256 KB 128 KB 128 KB 64 KB 64 KB
SAU 0x9000_0000 1 KB 1 KB 1 KB 1 KB 1 KB 1 KB 1 KB 1 KB
HSB
SRAM
0xA000_0000 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB
EBI SRAM
CS0
0xC000_0000 16 MB - 16 MB - 16 MB - 16 MB -
EBI SRAM
CS2
0xC800_0000 16 MB - 16 MB - 16 MB - 16 MB -
EBI SRAM
CS3
0xCC00_0000 16 MB - 16 MB - 16 MB - 16 MB -
EBI SRAM
/SDRAM
CS1
0xD000_0000 128 MB - 128 MB - 128 MB - 128 MB -
HSB-PB
Bridge C
0xFFFD_0000 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB
HSB-PB
Bridge B
0xFFFE_0000 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB
HSB-PB
Bridge A
0xFFFF_0000 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB 64 KB