Datasheet

84
9166DS–AVR-01/12
AT32UC3C
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Table 7-58. SDRAM Signal
(1)
Symbol Parameter Conditions Min Units
SDRAMC
1
SDCKE high before SDCK rising edge
V
VDD
= 3.0V,
drive strength of the pads set to
the highest,
external capacitor = 40pF on
SDRAM pins
except 8 pF on SDCK pins
7.7
ns
SDRAMC
2
SDCKE low after SDCK rising edge 10
SDRAMC
3
SDCKE low before SDCK rising edge 8.8
SDRAMC
4
SDCKE high after SDCK rising edge 10.9
SDRAMC
5
SDCS low before SDCK rising edge 8.1
SDRAMC
6
SDCS high after SDCK rising edge 11
SDRAMC
7
RAS low before SDCK rising edge 9.1
SDRAMC
8
RAS high after SDCK rising edge 10.3
SDRAMC
9
SDA10 change before SDCK rising edge 8.6
SDRAMC
10
SDA10 change after SDCK rising edge 9.8
SDRAMC
11
Address change before SDCK rising edge 6.7
SDRAMC
12
Address change after SDCK rising edge 6.8
SDRAMC
13
Bank change before SDCK rising edge 8.4
SDRAMC
14
Bank change after SDCK rising edge 9.5
SDRAMC
15
CAS low before SDCK rising edge 8.7
SDRAMC
16
CAS high after SDCK rising edge 10.4
SDRAMC
17
DQM change before SDCK rising edge 8.1
SDRAMC
18
DQM change after SDCK rising edge 9.3
SDRAMC
19
D0-D15 in setup before SDCK rising edge 7.0
SDRAMC
20
D0-D15 in hold after SDCK rising edge 0
SDRAMC
23
SDWE low before SDCK rising edge 9.1
SDRAMC
24
SDWE high after SDCK rising edge 10
SDRAMC
25
D0-D15 Out valid before SDCK rising edge 7.3
SDRAMC
26
D0-D15 Out valid after SDCK rising edge 5.7