Datasheet

83
9166DS–AVR-01/12
AT32UC3C
Figure 7-18. SMC Signals for NRD and NRW Controlled Accesses
(1)
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
7.9.8 SDRAM Signals
Note: 1. The maximum frequency of the SDRAMC interface is the same as the max frequency for the
HSB.
NRD
NCS
D0 - D15
NWE
A2-A25
A0/A1/NBS[3:0]
SMC7
SMC19 SMC20
SMC43
SMC37
SMC42
SMC8
SMC1
SMC2
SMC23
SMC24
SMC32
SMC7
SMC8
SMC6
SMC5
SMC4
SMC3
SMC9
SMC41
SMC40
SMC39
SMC38
SMC45
SMC9
SMC6
SMC5
SMC4
SMC3
SMC33
SMC30
SMC29
SMC26
SMC25
SMC31
SMC44
Table 7-57. SDRAM Clock Signal
Symbol Parameter Max
(1)
Units
1/(t
CPSDCK
) SDRAM Controller clock frequency f
cpu
MHz