Datasheet

80
9166DS–AVR-01/12
AT32UC3C
7.9.7 EBI Timings
See EBI I/O lines description for more details.
Note: 1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB.
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
2. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs rd hold length” or “nrd hold length”.
Table 7-52. SMC Clock Signal.
Symbol Parameter Max
(1)
Units
1/(t
CPSMC
) SMC Controller clock frequency f
cpu
MHz
Table 7-53. SMC Read Signals with Hold Settings
(1)
Symbol Parameter Conditions Min Units
NRD Controlled (READ_MODE = 1)
SMC
1
Data setup before NRD high
V
VDD
= 3.0V,
drive strength of the
pads set to the lowest,
external capacitor =
40pF
34.4
ns
SMC
2
Data hold after NRD high 0
SMC
3
NRD high to NBS0/A0 change
(2)
nrd hold length * tCPSMC - 1.5
SMC
4
NRD high to NBS1 change
(2)
nrd hold length * tCPSMC - 0
SMC
5
NRD high to NBS2/A1 change
(2)
nrd hold length * tCPSMC - 0
SMC
7
NRD high to A2 - A25 change
(2)
nrd hold length * tCPSMC - 5.9
SMC
8
NRD high to NCS inactive
(2)
(nrd hold length - ncs rd hold length) *
t
CPSMC - 1.3
SMC
9
NRD pulse width nrd pulse length * tCPSMC - 0.9
NRD Controlled (READ_MODE = 0)
SMC
10
Data setup before NCS high
V
VDD
= 3.0V,
drive strength of the
pads set to the lowest,
external capacitor =
40pF
36.1
ns
SMC
11
Data hold after NCS high 0
SMC
12
NCS high to NBS0/A0 change
(2)
ncs rd hold length * tCPSMC - 3.2
SMC
13
NCS high to NBS0/A0 change
(2)
ncs rd hold length * tCPSMC - 2.2
SMC
14
NCS high to NBS2/A1 change
(2)
ncs rd hold length * tCPSMC - 1.2
SMC
16
NCS high to A2 - A25 change
(2)
ncs rd hold length * tCPSMC - 7.6
SMC
17
NCS high to NRD inactive
(2)
(ncs rd hold length - nrd hold length) *
t
CPSMC - 2.4
SMC
18
NCS pulse width ncs rd pulse length * tCPSMC - 3.3