Datasheet

9166DS–AVR-01/12

AT32UC3C

7.9.6 JTAG Timing

Figure 7-16. JTAG Interface Signals

Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-

cess technology. These values are not covered by test limits in production.

JTAG2

JTAG3

JTAG1

JTAG4

JTAG0

TMS/TDI

TCK

TDO

JTAG5

JTAG6

JTAG7 JTAG8

JTAG9

JTAG10

Boundary

Scan Inputs

Boundary

Scan Outputs

Table 7-51. JTAG Timings

(1)

Symbol Parameter Conditions Min Max Units

JTAG0 TCK Low Half-period

external

capacitor =

40pF

23 ns

JTAG1 TCK High Half-period 9 ns

JTAG2 TCK Period 31 ns

JTAG3 TDI, TMS Setup before TCK High 7 ns

JTAG4 TDI, TMS Hold after TCK High 0 ns

JTAG5 TDO Hold Time 13.5 ns

JTAG6 TCK Low to TDO Valid 23 ns

JTAG7 Boundary Scan Inputs Setup Time 0 ns

JTAG8 Boundary Scan Inputs Hold Time 4.5 ns

JTAG9 Boundary Scan Outputs Hold Time 12 ns

JTAG10 TCK to Boundary Scan Outputs Valid 19 ns