Datasheet

75
9166DS–AVR-01/12
AT32UC3C
Figure 7-12. SPI Master Mode With (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Maximum SPI Frequency, Master Output
The maximum SPI master output frequency is given by the following formula:
Where is the MOSI delay, SPI2 or SPI5 depending on CPOL and NCPHA. is the
maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the
maximum frequency of the pins.
Maximum SPI Frequency, Master Input
The maximum SPI master input frequency is given by the following formula:
Where is the MISO setup and hold time, SPI0 + SPI1 or SPI3 + SPI4 depending on
CPOL and NCPHA. is the SPI slave response time. Please refer to the SPI slave
datasheet for .
SPI3 SPI4
MISO
SPCK
MOSI
SPI5
Table 7-48. SPI Timing, Master Mode
(1)
Symbol Parameter Conditions Min Max Units
SPI0 MISO setup time before SPCK rises
external
capacitor =
40pF
30.5+ (t
CLK_SPI
)/2 ns
SPI1 MISO hold time after SPCK rises 0 ns
SPI2 SPCK rising to MOSI delay 11.5 ns
SPI3 MISO setup time before SPCK falls 30.5 + (t
CLK_SPI
)/2 ns
SPI4 MISO hold time after SPCK falls 0 ns
SPI5 SPCK falling to MOSI delay 11.5 ns
f
SPCKMAX
MIN f
PINMAX
1
SPIn
------------(,)=
SPIn
f
PINMAX
f
SPCKMAX
1
SPIn t
VALID
+
----------------------------------- -=
SPIn
t
VALID
t
VALID