Datasheet

73
9166DS–AVR-01/12
AT32UC3C
Figure 7-9. USART in SPI Slave Mode With (CPOL= CPHA= 0) or (CPOL= CPHA= 1)
Figure 7-10. USART in SPI Slave Mode NPCS Timing
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
2. Where:
USPI10 USPI11
MISO
SPCK
MOSI
USPI9
USPI14
USPI12
USPI15
USPI13
NSS
SPCK, CPOL=0
SPCK, CPOL=1
Table 7-47. USART in SPI mode Timing, Slave Mode
(1)
Symbol Parameter Conditions Min Max Units
USPI6 SPCK falling to MISO delay
external
capacitor =
40pF
28.5 ns
USPI7 MOSI setup time before SPCK rises t
SAMPLE
(2)
+ t
CLK_USART
ns
USPI8 MOSI hold time after SPCK rises 0 ns
USPI9 SPCK rising to MISO delay 30 ns
USPI10 MOSI setup time before SPCK falls t
SAMPLE
(2)
+ t
CLK_USART
ns
USPI11 MOSI hold time after SPCK falls 0 ns
USPI12 NSS setup time before SPCK rises 35 ns
USPI13 NSS hold time after SPCK falls 0 ns
USPI14 NSS setup time before SPCK falls 35 ns
USPI15 NSS hold time after SPCK rises 0 ns
t
SAMPLE
t
SPCK
t
SPCK
2 t
CLKUSART
×
------------------------------------
1
2
---+
⎝⎠
⎛⎞
t
CLKUSART
×–=