Datasheet

71
9166DS–AVR-01/12
AT32UC3C
7.9.3 USART in SPI Mode Timing
7.9.3.1 Master mode
Figure 7-6. USART in SPI Master Mode With (CPOL= CPHA= 0) or (CPOL= CPHA= 1)
Figure 7-7. USART in SPI Master Mode With (CPOL= 0 and CPHA= 1) or (CPOL= 1 and
CPHA= 0)
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
2. Where:
USPI0 USPI1
MISO
SPCK
MOSI
USPI2
USPI3 USPI4
MISO
SPCK
MOSI
USPI5
Table 7-46. USART in SPI Mode Timing, Master Mode
(1)
Symbol Parameter Conditions Min Max Units
USPI0 MISO setup time before SPCK rises
external
capacitor =
40pF
27.5+ t
SAMPLE
(2)
ns
USPI1 MISO hold time after SPCK rises 0 ns
USPI2 SPCK rising to MOSI delay 12 ns
USPI3 MISO setup time before SPCK falls 27.5+ t
SAMPLE
(2)
ns
USPI4 MISO hold time after SPCK falls 0 ns
USPI5 SPCK falling to MOSI delay 12.5 ns
t
SAMPLE
t
SPCK
t
SPCK
2 t
CLKUSART
×
------------------------------------
1
2
---
⎝⎠
⎛⎞
t
CLKUSART
×–=