Datasheet

69
9166DS–AVR-01/12
AT32UC3C
7.9 Timing Characteristics
7.9.1 Startup, Reset, and Wake-up Timing
The startup, reset, and wake-up timings are calculated using the following formula:
Where and are found in Table 7-44. is the delay relative to RCSYS,
is the period of the CPU clock. If another clock source than RCSYS is selected as CPU
clock the startup time of the oscillator, , must be added to the wake-up time in the
stop, deepstop, and static sleep modes. Please refer to the source for the CPU clock in the
”Oscillator Characteristics” on page 56 for more details about oscillator startup times.
tt
CONST
N
CPU
t
CPU
×+=
t
CONST
N
CPU
t
CONST
t
CPU
t
OSCSTART
Table 7-44. Maximum Reset and Wake-up Timing
Parameter Measuring Max (in µs) Max
Startup time from power-up, using
regulator
VDDIN_5 rising (10 mV/ms)
Time from V
VDDIN_5
=0 to the first instruction entering
the decode stage of CPU. VDDCORE is supplied by
the internal regulator.
2600 0
Startup time from reset release
Time from releasing a reset source (except POR,
BOD18, and BOD33) to the first instruction entering
the decode stage of CPU.
1240 0
Wake-up
Idle
From wake-up event to the first instruction entering
the decode stage of the CPU.
019
Frozen 268 209
Standby 268 209
Stop 268+ 212
Deepstop 268+ 212
Static 268+ 212
t
CONST
N
CPU
t
OSCSTART
t
OSCSTART
t
OSCSTART