Datasheet

66
9166DS–AVR-01/12
AT32UC3C
Note: 1. The measures are done without any I/O activity on VDDANA/GNDANA power domain.
7.8.7 Digital to Analog Converter (DAC) Characteristics
RES Resolution Differential mode,
V
VDDANA
= 5V,
V
ADCREF0
= 3V,
ADCFIA.SEQCFGn.SRES = 1,
S/H gain from 1 to 16
(F
adc
= 1.5MHz)
10 Bit
INL Integral Non-Linearity 2LSB
DNL Differential Non-Linearity 2LSB
Offset error -30 30 mV
Gain error -30 30 mV
Table 7-36. ADC and S/H Transfer Characteristics (Continued)10-bit Resolution Mode and S/H gain from 1 to 16
(1)
Symbol Parameter Conditions Min Typ Max Units
Table 7-37. Channel Conversion Time and DAC Clock
Symbol Parameter Conditions Min Typ Max Units
f
DAC
DAC clock frequency 1MHz
t
STARTUP
Startup time 3µs
t
CONV
Conversion time (latency)
No S/H enabled, internal DAC 1 µs
One S/H 1.5 µs
Two S/H 2 µs
Throughput rate 1/t
CONV
MSPS
Table 7-38. External Voltage Reference Input
Symbol Parameter Conditions Min Typ Max Units
V
DACREF
DACREF input voltage range 1.2 V
VDDANA
-0.7 V
Table 7-39. DAC Outputs
Symbol Parameter Conditions Min Typ Max Units
Output range
with external DAC reference 0.2 V
DACREF
V
with internal DAC reference 0.2 V
VDDANA
-0.7
C
LOAD
Output capacitance 0 100 pF
R
LOAD
Output resitance 2 kΩ