Datasheet

62
9166DS–AVR-01/12
AT32UC3C
7.8.6 Analog to Digital Converter (ADC) and sample and hold (S/H) Characteristics
Table 7-27. ADC and S/H characteristics
Symbol Parameter Conditions Min Typ Max Units
f
ADC
ADC clock
frequency
12-bit resolution mode, V
VDDANA
= 3V 1.2
MHz
10-bit resolution mode, V
VDDANA
= 3V 1.6
8-bit resolution mode, V
VDDANA
= 3V 2.2
12-bit resolution mode, V
VDDANA
= 4.5V 1.5
10-bit resolution mode, V
VDDANA
= 4.5V 2
8-bit resolution mode, V
VDDANA
= 4.5V 2.4
t
STARTUP
Startup time
ADC cold start-up 1 ms
ADC hot start-up 24
ADC clock
cycles
t
CONV
Conversion time
(latency)
(ADCIFA.SEQCFGn.SRES)/2 + 2,
ADCIFA.CFG.SHD = 1
68
ADC clock
cycles
(ADCIFA.SEQCFGn.SRES)/2 + 3,
ADCIFA.CFG.SHD = 0
79
Throughput rate
12-bit resolution,
ADC clock = 1.2 MHz, V
VDDANA
= 3V
1.2
MSPS
10-bit resolution,
ADC clock = 1.6 MHz, V
VDDANA
= 3V
1.6
12-bit resolution,
ADC clock = 1.5 MHz, V
VDDANA
= 4.5V
1.5
10-bit resolution,
ADC clock = 2 MHz, V
VDDANA
= 4.5V
2
Table 7-28. ADC Reference Voltage
Symbol Parameter Conditions Min Typ Max
Unit
s
V
ADCREF0
ADCREF0 input voltage range
5V Range 1 3.5
V
3V Range 1 V
VDDANA
-0.7
V
ADCREF1
ADCREF1 input voltage range
5V Range 1 3.5
V
3V Range 1 V
VDDANA
-0.7
V
ADCREFP
ADCREFP input voltage
5V Range - Voltage reference
applied on ADCREFP
13.5
V
3V Range - Voltage reference
applied on ADCREFP
1V
VDDANA
-0.7
V
ADCREFN
ADCREFN input voltage
Voltage reference applied on
ADCREFN
GNDANA V
Internal 1V reference 1.0 V
Internal 0.6*VDDANA reference 0.6*V
VDDANA
V