Datasheet

59
9166DS–AVR-01/12
AT32UC3C
7.7 Flash Characteristics
Table 7-15 gives the device maximum operating frequency depending on the number of flash
wait states. The FSW bit in the FLASHC FSR register controls the number of wait states used
when accessing the flash memory.
Table 7-15. Maximum Operating Frequency
Flash Wait States Read Mode Maximum Operating Frequency
0 1 cycle 25MHz
1 2 cycles 50MHz
Table 7-16. Flash Characteristics
Symbol Parameter Conditions Min Typ Max Unit
t
FPP
Page programming time
f
CLK_HSB
= 50MHz
17
ms
t
FPE
Page erase time 17
t
FFP
Fuse programming time 1.3
t
FEA
Full chip erase time (EA) 18.3
t
FCE
JTAG chip erase time (CHIP_ERASE) f
CLK_HSB
= 115kHz 640
Table 7-17. Flash Endurance and Data Retention
Symbol Parameter Conditions Min Typ Max Unit
N
FARRAY
Array endurance (write/page) 10k cycles
N
FFUSE
General Purpose fuses endurance (write/bit) 500 cycles
t
RET
Data retention 15 years