Datasheet

47
9166DS–AVR-01/12
AT32UC3C
Figure 6-2. 3 Single Power Supply Mode
6.1.4 Power-up Sequence
6.1.4.1 Maximum Rise Rate
To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values
described in Table 7-2 on page 50.
Recommended order for power supplies is also described in this table.
6.1.4.2 Minimum Rise Rate
The integrated Power-Reset circuitry monitoring the powering supply requires a minimum rise
rate for the VDDIN_5 power supply.
See Table 7-2 on page 50 for the minimum rise rate value.
If the application can not ensure that the minimum rise rate condition for the VDDIN power sup-
ply is met, the following configuration can be used:
• A logic “0” value is applied during power-up on pin RESET_N until:
– VDDIN_5 rises above 4.5V in 5V single supply mode.
– VDDIN_33 rises above 3V in 3.3V single supply mode.
VDDIN_33
CPU
Peripherals
Memories
SCIF, BOD,
RCSYS
3.3V
Reg
Analog: ADC, AC, DAC, ...
VDDIN_5
VDDANA GNDANA
VDDCORE
C
OUT2
C
OUT1
GNDCORE
GNDPLL
PLL
BOD50
BOD33
1.8V
Reg
BOD18
POR
+
-
3.0-
3.6V
C
IN2
C
IN1
VDDIO1
VDDIO2
VDDIO3
GNDIO1
GNDIO2
GNDIO3